| /src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/ |
| MCExternalSymbolizer.cpp | 100 const MCExpr *Sub = nullptr;
105 Sub = MCSymbolRefExpr::create(Sym, Ctx);
107 Sub = MCConstantExpr::create((int)SymbolicOp.SubtractSymbol.Value, Ctx);
116 if (Sub) {
119 LHS = MCBinaryExpr::createSub(Add, Sub, Ctx);
121 LHS = MCUnaryExpr::createMinus(Sub, Ctx);
|
| /src/external/apache2/llvm/dist/llvm/examples/Fibonacci/ |
| fibonacci.cpp | 83 Value *Sub = BinaryOperator::CreateSub(ArgX, One, "arg", RecurseBB);
84 CallInst *CallFibX1 = CallInst::Create(FibF, Sub, "fibx1", RecurseBB);
88 Sub = BinaryOperator::CreateSub(ArgX, Two, "arg", RecurseBB);
89 CallInst *CallFibX2 = CallInst::Create(FibF, Sub, "fibx2", RecurseBB);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonExpandCondsets.cpp | 180 Sub(Op.getSubReg()) {}
181 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
184 return Reg == RR.Reg && Sub == RR.Sub;
188 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
192 unsigned Sub;
199 unsigned getMaskForSub(unsigned Sub);
201 LaneBitmask getLaneMask(Register Reg, unsigned Sub);
261 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {
[all...] |
| HexagonBitSimplify.cpp | 404 // For a register ref (pair Reg:Sub), set Begin to the position of the LSB
405 // of Sub in Reg, and set Width to the size of Sub in bits. Return true,
410 if (RR.Sub == 0) {
422 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi)
894 // Calculate the register class that matches Reg:Sub. For example, if
902 if (RR.Sub == 0)
907 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void {
909 assert(Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_lo) |
[all...] |
| BitTracker.cpp | 331 // to a given reference reg:sub. There can be several such classes, and
336 // 2. find a physical register PhysS that corresponds to PhysR:RR.Sub,
339 const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub);
344 (RR.Sub == 0) ? RR.Reg.asMCReg() : TRI.getSubReg(RR.Reg, RR.Sub);
366 if (!RR.Sub)
368 BitMask M = mask(RR.Reg, RR.Sub);
382 assert(RR.Sub == 0 && "Unexpected sub-register in definition");
707 BT::BitMask BT::MachineEvaluator::mask(Register Reg, unsigned Sub) const
[all...] |
| HexagonBitTracker.h | 39 BitTracker::BitMask mask(Register Reg, unsigned Sub) const override;
|
| HexagonBlockRanges.h | 37 unsigned Sub;
40 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
|
| BitTracker.h | 142 RegisterRef(Register R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
144 : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
147 unsigned Sub;
458 // Return a sub-register mask that indicates which bits in Reg belong
459 // to the subregister Sub. These bits are assumed to be contiguous in
460 // the super-register, and have the same ordering in the sub-register
462 // Sub == 0, in this case, the function should return a mask that spans
465 virtual BitMask mask(Register Reg, unsigned Sub) const;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64ExternalSymbolizer.cpp | 182 const MCExpr *Sub = nullptr;
187 Sub = MCSymbolRefExpr::create(Sym, Ctx);
189 Sub = MCConstantExpr::create(SymbolicOp.SubtractSymbol.Value, Ctx);
198 if (Sub) {
201 LHS = MCBinaryExpr::createSub(Add, Sub, Ctx);
203 LHS = MCUnaryExpr::createMinus(Sub, Ctx);
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| DivRemPairs.cpp | 271 Instruction *Sub = BinaryOperator::CreateSub(X, Mul);
283 // %rem = sub %x, %mul
285 // If the division dominates, it's already in the right place. The mul+sub
298 // %rem = sub %x, %mul
306 Sub->insertAfter(Mul);
315 // %rem = sub %x, %mul // %rem = undef - undef = undef
321 Sub->setOperand(0, FrX);
332 // (sub X, (mul (div X, Y), Y)
333 Sub->setName(RemInst->getName() + ".decomposed");
336 RemInst = Sub;
[all...] |
| Reassociate.cpp | 721 // Not the last operation. The left-hand side will be a sub-expression
906 if (TheNeg->getOpcode() == Instruction::Sub) {
983 for (auto Op : {Instruction::Add, Instruction::Sub, Instruction::Mul,
1019 static bool ShouldBreakUpSubtract(Instruction *Sub) {
1021 if (match(Sub, m_Neg(m_Value())) || match(Sub, m_FNeg(m_Value())))
1025 if (isa<UndefValue>(Sub->getOperand(1)))
1030 Value *V0 = Sub->getOperand(0);
1032 isReassociableOp(V0, Instruction::Sub, Instruction::FSub))
1034 Value *V1 = Sub->getOperand(1)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Support/ |
| CommandLine.cpp | 187 // If we're adding this to all sub-commands, add it to the ones that have
190 for (auto *Sub : RegisteredSubCommands) {
191 if (SC == Sub)
193 addLiteralOption(Opt, Sub, Name);
243 // If we're adding this to all sub-commands, add it to the ones that have
246 for (auto *Sub : RegisteredSubCommands) {
247 if (SC == Sub)
249 addOption(O, Sub);
274 SubCommand &Sub = *SC;
275 auto End = Sub.OptionsMap.end()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| CalcSpillWeights.cpp | 49 unsigned Sub, HSub;
52 Sub = MI->getOperand(0).getSubReg();
56 Sub = MI->getOperand(1).getSubReg();
65 return Sub == HSub ? HReg : Register();
72 // Check if reg:sub matches so that a super register could be hinted.
73 if (Sub)
74 return TRI.getMatchingSuperReg(CopiedPReg, Sub, rc);
|
| /src/external/apache2/llvm/dist/llvm/examples/ParallelJIT/ |
| ParallelJIT.cpp | 114 Value *Sub = BinaryOperator::CreateSub(ArgX, One, "arg", RecurseBB);
115 Value *CallFibX1 = CallInst::Create(FibF, Sub, "fibx1", RecurseBB);
118 Sub = BinaryOperator::CreateSub(ArgX, Two, "arg", RecurseBB);
119 Value *CallFibX2 = CallInst::Create(FibF, Sub, "fibx2", RecurseBB);
|
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| ReplaceConstant.cpp | 34 case Instruction::Sub:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86WinAllocaExpander.cpp | 44 enum Lowering { TouchAndSub, Sub, Probe };
105 return Sub;
163 case Sub:
230 case Sub:
238 // Sub.
256 // Sub
|
| X86PartialReduction.cpp | 120 // SelectionDAG has limited support for truncating through an add or sub if
191 auto *Sub = dyn_cast<BinaryOperator>(LHS);
192 if (!Sub || Sub->getOpcode() != Instruction::Sub)
207 Value *Op0 = getZeroExtendedVal(Sub->getOperand(0));
208 Value *Op1 = getZeroExtendedVal(Sub->getOperand(1));
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/AggressiveInstCombine/ |
| TruncInstCombine.cpp | 59 case Instruction::Sub:
125 case Instruction::Sub:
219 // sub-optimal code.
355 case Instruction::Sub:
|
| /src/sys/external/bsd/compiler_rt/dist/lib/sanitizer_common/ |
| sanitizer_allocator_stats.h | 39 void Sub(AllocatorStat i, uptr v) {
|
| /src/external/gpl3/gcc/dist/libsanitizer/sanitizer_common/ |
| sanitizer_allocator_stats.h | 33 void Sub(AllocatorStat i, uptr v) {
|
| /src/external/gpl3/gcc.old/dist/libsanitizer/sanitizer_common/ |
| sanitizer_allocator_stats.h | 38 void Sub(AllocatorStat i, uptr v) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUAtomicOptimizer.cpp | 126 case AtomicRMWInst::Sub:
179 Op = AtomicRMWInst::Sub;
258 case AtomicRMWInst::Sub:
259 return B.CreateBinOp(Instruction::Sub, LHS, RHS);
433 case AtomicRMWInst::Sub:
533 Op == AtomicRMWInst::Sub ? AtomicRMWInst::Add : Op;
561 case AtomicRMWInst::Sub: {
664 case AtomicRMWInst::Sub:
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| RelLookupTableConverter.cpp | 113 Constant *Sub = llvm::ConstantExpr::getSub(Target, Base);
115 llvm::ConstantExpr::getTrunc(Sub, Type::getInt32Ty(M.getContext()));
|
| /src/external/apache2/llvm/dist/clang/lib/Basic/ |
| Module.cpp | 321 for (submodule_iterator Sub = Current->submodule_begin(),
323 Sub != SubEnd; ++Sub) {
324 if (needUpdate(*Sub))
325 Stack.push_back(*Sub);
|
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| TypeBasedAliasAnalysis.cpp | 764 SmallVector<Metadata *, 3> Sub;
781 Sub.push_back(ConstantAsMetadata::get(
783 Sub.push_back(ConstantAsMetadata::get(
785 Sub.push_back(MD->getOperand(i + 2));
787 return MDNode::get(MD->getContext(), Sub);
|
