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    Searched refs:Sub1 (Results 1 - 13 of 13) sorted by relevancy

  /src/external/bsd/libc++/dist/libcxxrt/test/
test_typeinfo.cc 24 struct Sub1 : public Root
29 struct Sub2 : public Sub1
90 TEST(12 == b->test, "Casting Sub1 to superclass");
91 ((Sub1*)(s2))->a = 12;
92 TEST(12 == dynamic_cast<Sub1*>(s2)->a, "Casting Sub2 -> Sub1");
110 TEST(0 == dynamic_cast<Sub1*>(b2), "Casting Root to Sub1 (0 expected)");
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp 245 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32,
249 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
  /src/external/apache2/llvm/dist/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
BasicValueFactory.h 211 const llvm::APSInt &Sub1(const llvm::APSInt &V) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 642 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)};
789 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
1023 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
1028 DL, MVT::i32, LHS, Sub1);
1033 DL, MVT::i32, RHS, Sub1);
1066 Sub1,
1713 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
1718 DL, MVT::i32, N0, Sub1);
    [all...]
AMDGPULegalizerInfo.cpp 2933 auto Sub1 = B.buildMerge(S64, {Sub1_Lo, Sub1_Hi});
2988 B.buildICmp(CmpInst::ICMP_NE, S1, C3, Zero32), Sel2, Sub1);
AMDGPUISelLowering.cpp 1880 SDValue Sub1 = DAG.getBitcast(VT,
1931 SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCCodeEmitter.cpp 436 const MCInst *Sub1 = MI.getOperand(1).getInst();
442 unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBitSimplify.cpp 438 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm();
444 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo));
445 if (Sub1 == SubLo && Sub2 == SubHi) {
450 if (Sub1 == SubHi && Sub2 == SubLo) {
HexagonConstPropagation.cpp 1957 unsigned Sub1 = MI.getOperand(2).getImm();
1962 if (Sub1 != SubLo && Sub1 != SubHi)
1966 assert(Sub1 != Sub2);
1967 bool LoIs1 = (Sub1 == SubLo);
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.cpp 1348 auto compose = [&SubRegAction] (const CodeGenSubRegIndex *Sub1,
1351 const RegMap &Img1 = SubRegAction.at(Sub1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 5550 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
5554 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
TargetLowering.cpp 8290 SDValue Sub1 = DAG.getNode(ISD::SUB, dl, VT, Quot,
8294 Sub1, Quot);
DAGCombiner.cpp 19971 SDValue Sub1 = getSubVectorSrc(Bop1, Index, SubVT);
19976 if (!Sub0 || !Sub1)
19982 return DAG.getNode(BinOpcode, SDLoc(Extract), SubVT, Sub0, Sub1,

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