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    Searched refs:SubRC (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
RegisterBank.cpp 46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
48 if (!RC.hasSubClassEq(&SubRC))
53 assert(getSize() >= TRI.getRegSizeInBits(SubRC) &&
55 assert(covers(SubRC) && "Not all subclasses are covered");
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetRegisterInfo.cpp 200 const TargetRegisterClass *SubRC = getRegClass(It.getID());
201 if (SubRC->isAllocatable())
202 return SubRC;
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.cpp 952 CodeGenRegisterClass &SubRC = *I2;
953 if (RC.SubClasses.test(SubRC.EnumValue))
955 if (!testSubClass(&RC, &SubRC))
957 // SubRC is a sub-class. Grap all its sub-classes so we won't have to
959 RC.SubClasses |= SubRC.SubClasses;
2212 CodeGenRegisterClass *SubRC =
2215 RC->setSubClassWithSubReg(&SubIdx, SubRC);
2257 CodeGenRegisterClass &SubRC = *I;
2258 if (SubRC.Artificial)
2260 // Topological shortcut: SubRC members have the wrong shape
    [all...]
CodeGenRegisters.h 401 CodeGenRegisterClass *SubRC) {
402 SubClassWithSubReg[SubIdx] = SubRC;
RISCVCompressInstEmitter.cpp 164 const CodeGenRegisterClass &SubRC = Target.getRegisterClass(DagOpType);
165 return RC.hasSubClass(&SubRC);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.h 91 const TargetRegisterClass &SubRC,
SIRegisterInfo.h 200 /// subregister exists with class \p SubRC with subregister index \p
205 const TargetRegisterClass *SubRC,
SIInstrInfo.h 67 const TargetRegisterClass *SubRC) const;
73 const TargetRegisterClass *SubRC) const;
SIRegisterInfo.cpp 2154 const TargetRegisterClass *SubRC,
2158 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx);
SIInstrInfo.cpp 3810 const TargetRegisterClass *SubRC =
3812 RC = RI.getCompatibleSubRegClass(RC, SubRC, MO.getSubReg());
3814 RC = SubRC;
4534 const TargetRegisterClass *SubRC)
4538 Register SubReg = MRI.createVirtualRegister(SubRC);
4567 const TargetRegisterClass *SubRC) const {
4578 SubIdx, SubRC);
AMDGPUInstructionSelector.cpp 233 const TargetRegisterClass &SubRC,
238 Register DstReg = MRI->createVirtualRegister(&SubRC);
SIISelLowering.cpp 4057 const TargetRegisterClass *SubRC =
4060 MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC);
4062 MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 5293 const TargetRegisterClass *SubRC;
5297 SubRC = &AArch64::GPR32spRegClass;
5303 SubRC = &AArch64::GPR64spRegClass;
5308 Register NewVR = MRI.createVirtualRegister(SubRC);

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