| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsOptionRecord.cpp | 77 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) {
78 unsigned EncVal = MCRegInfo->getEncodingValue(SubReg);
81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg))
83 else if (COP0RegClass->contains(SubReg))
86 else if (FGR32RegClass->contains(SubReg) ||
87 FGR64RegClass->contains(SubReg) ||
88 AFGR64RegClass->contains(SubReg) ||
89 MSA128BRegClass->contains(SubReg))
91 else if (COP2RegClass->contains(SubReg))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 104 static bool isGPR64(unsigned Reg, unsigned SubReg,
106 if (SubReg)
113 static bool isFPR64(unsigned Reg, unsigned SubReg,
117 SubReg == 0) ||
119 SubReg == AArch64::dsub);
121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
122 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub);
129 unsigned &SubReg) {
130 SubReg = 0;
138 SubReg = AArch64::dsub
[all...] |
| AArch64RegisterInfo.h | 134 unsigned SubReg, const TargetRegisterClass *DstRC,
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 196 unsigned SubReg = *SubRegs;
197 MachineInstr *Def = PhysRegDef[SubReg];
202 LastDefReg = SubReg;
250 unsigned SubReg = *SubRegs;
251 if (Processed.count(SubReg))
253 if (PartDefRegs.count(SubReg))
257 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
260 PhysRegDef[SubReg] = LastPartialDef;
261 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
289 unsigned SubReg = *SubRegs
[all...] |
| LiveIntervalCalc.cpp | 68 unsigned SubReg = MO.getSubReg();
69 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) {
70 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
168 unsigned SubReg = MO.getSubReg();
169 if (SubReg != 0) {
170 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg);
|
| PeepholeOptimizer.cpp | 297 ValueTrackerResult(Register Reg, unsigned SubReg) {
298 addSource(Reg, SubReg);
332 assert(Idx < getNumSources() && "SubReg source out of index");
333 return RegSrcs[Idx].SubReg;
455 /// reachable uses of the source with the subreg of the result.
655 /// for the value defined by \p Reg and \p SubReg.
662 /// share the same register file as \p Reg and \p SubReg. The client should
687 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII);
737 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC,
738 CurSrcPair.SubReg))
[all...] |
| DetectDeadLanes.cpp | 174 unsigned SubReg = MI.getOperand(2).getImm();
175 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx);
424 unsigned SubReg = MO.getSubReg();
447 if (SubReg == 0)
450 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
457 unsigned SubReg = MO.getSubReg();
458 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
|
| MachineInstrBundle.cpp | 198 unsigned SubReg = *SubRegs;
199 if (LocalDefSet.insert(SubReg).second)
200 LocalDefs.push_back(SubReg);
|
| LiveIntervals.cpp | 577 unsigned SubReg = MO.getSubReg();
578 if (SubReg != 0) {
579 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
791 unsigned SubReg = MO.getSubReg();
792 LaneBitmask UseMask = SubReg ? TRI->getSubRegIndexLaneMask(SubReg)
1031 unsigned SubReg = MO.getSubReg();
1032 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg)
1193 // We merge OldIdxOut and its successor. As we're dealing with subreg
[all...] |
| ScheduleDAGInstrs.cpp | 340 for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) {
341 if (Uses.contains(*SubReg))
342 Uses.eraseAll(*SubReg);
344 Defs.eraseAll(*SubReg);
376 unsigned SubReg = MO.getSubReg();
377 if (SubReg == 0)
379 return TRI->getSubRegIndexLaneMask(SubReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 45 MCRegister SubReg) const {
46 assert(SubReg && SubReg < getNumRegs() && "This is not a register");
51 if (*Subs == SubReg)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.h | 56 unsigned SubReg,
|
| AVRRegisterInfo.cpp | 281 unsigned SubReg,
290 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.h | 37 /// First index represents subreg size from 1 to 16 DWORDs.
44 // First index is subreg size: 32, 64, 96, 128, 160, 192, 224, 256, 512.
246 unsigned SubReg,
297 MachineInstr *findReachingDef(Register Reg, unsigned SubReg,
309 // The assumption is that every lo16 subreg is an even bit and every hi16
318 // \returns a DWORD offset of a \p SubReg
319 unsigned getChannelFromSubReg(unsigned SubReg) const {
320 return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0;
323 // \returns a DWORD size of a \p SubReg
[all...] |
| SIPreAllocateWWMRegs.cpp | 132 const unsigned SubReg = MO.getSubReg();
133 if (SubReg != 0) {
134 PhysReg = TRI->getSubReg(PhysReg, SubReg);
|
| SIShrinkInstructions.cpp | 389 Register Reg, unsigned SubReg,
399 LaneBitmask Overlap = TRI.getSubRegIndexLaneMask(SubReg) &
409 unsigned Reg, unsigned SubReg,
411 return instAccessReg(MI->uses(), Reg, SubReg, TRI);
415 unsigned Reg, unsigned SubReg,
417 return instAccessReg(MI->defs(), Reg, SubReg, TRI);
562 .addDef(X1.Reg, 0, X1.SubReg)
563 .addDef(Y1.Reg, 0, Y1.SubReg)
564 .addReg(Y1.Reg, 0, Y1.SubReg)
565 .addReg(X1.Reg, 0, X1.SubReg).getInstr()
[all...] |
| SIRegisterInfo.cpp | 282 "getNumCoveredRegs() will not work with generated subreg masks!");
1144 Register SubReg = e == 1
1190 // current SubReg has been already spilled into AGPRs by the loop above.
1197 SubReg = Register(getSubReg(ValueReg,
1203 unsigned FinalReg = SubReg;
1217 .addReg(SubReg, getKillRegState(IsKill));
1222 SubReg = TmpReg;
1232 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill));
1321 Register SubReg =
1333 .addReg(SubReg, getKillRegState(UseKill)
[all...] |
| R600OptimizeVectorRegisters.cpp | 11 /// common data and/or have enough undef subreg using swizzle abilities.
196 unsigned SubReg = (*It).first;
203 .addReg(SubReg)
205 UpdatedRegToChan[SubReg] = Chan;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.h | 25 // Generic (pseudo) subreg indices for use with getHexagonSubRegIndex.
60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 254 for (const auto &SubReg : SubRegs) {
255 CodeGenRegister *SR = SubReg.second;
301 // Expand any composed subreg indices.
303 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
304 // expanded subreg indices recursively.
318 // Add I->second as a name for the subreg SRI->second, assuming it is
331 // Consider this subreg sequence:
342 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
348 for (const auto &SubReg : Map
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetInstrInfo.h | 244 /// expected the pre-extension value is available as a subreg of the result
382 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
463 /// Used to give some type checking when modeling Reg:SubReg.
466 unsigned SubReg;
468 RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)
469 : Reg(Reg), SubReg(SubReg) {}
472 return Reg == P.Reg && SubReg == P.SubReg;
485 RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0
[all...] |
| MachineInstrBuilder.h | 98 unsigned SubReg = 0) const {
108 SubReg,
117 unsigned SubReg = 0) const {
118 return addReg(RegNo, Flags | RegState::Define, SubReg);
124 unsigned SubReg = 0) const {
127 return addReg(RegNo, Flags, SubReg);
|
| TargetRegisterInfo.h | 241 const char *const *SubRegIndexNames; // Names of subreg indexes.
590 // subreg index DefSubReg, reading from another source with class SrcRC and
623 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
628 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
1025 unsigned SubReg,
1115 unsigned SubReg = 0;
1135 unsigned getSubReg() const { return SubReg; }
1146 SubReg = *Idx++;
1147 if (!SubReg)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.h | 23 // Return the subreg to use for referring to the even and odd registers
159 unsigned SubReg,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 543 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP))
544 Reserved.set(SubReg);
550 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP))
551 Reserved.set(SubReg);
555 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP))
556 Reserved.set(SubReg);
569 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr))
570 Reserved.set(SubReg);
|
