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    Searched refs:SubReg0 (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64AdvSIMDScalarPass.cpp 206 unsigned SubReg0;
212 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0);
298 unsigned Src0 = 0, SubReg0;
305 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0);
342 SubReg0 = 0;
363 .addReg(Src0, getKillRegState(KillSrc0), SubReg0)
AArch64ISelLowering.cpp 16611 SDValue SubReg0 = DAG.getTargetConstant(AArch64::sube64, dl, MVT::i32);
16613 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 };
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetInstrInfo.cpp 187 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
210 SubReg0 = SubReg2;
215 SubReg0 = SubReg1;
229 CommutedMI->getOperand(0).setSubReg(SubReg0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 1833 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32);
1835 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1844 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
1846 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1855 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
1857 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1866 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
1868 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1878 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
1882 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1
    [all...]
ARMISelLowering.cpp 9763 SDValue SubReg0 = DAG.getTargetConstant(ARM::gsub_0, dl, MVT::i32);
9765 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 };
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.cpp 68 unsigned RegClassID, unsigned SubReg0) {
78 Ops.push_back(CurDAG.getTargetConstant(SubReg0 + I, DL, MVT::i32));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 780 SDValue RC, SubReg0, SubReg1;
784 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
788 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
793 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,

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