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    Searched refs:SubReg1 (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64AdvSIMDScalarPass.cpp 207 unsigned SubReg1;
225 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1);
299 unsigned Src1 = 0, SubReg1;
324 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1);
348 SubReg1 = 0;
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1);
AArch64ISelLowering.cpp 16612 SDValue SubReg1 = DAG.getTargetConstant(AArch64::subo64, dl, MVT::i32);
16613 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 };
16660 unsigned SubReg1 = AArch64::sube64, SubReg2 = AArch64::subo64;
16662 std::swap(SubReg1, SubReg2);
16663 SDValue Lo = DAG.getTargetExtractSubreg(SubReg1, SDLoc(N), MVT::i64,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetInstrInfo.cpp 188 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
215 SubReg0 = SubReg1;
233 CommutedMI->getOperand(Idx2).setSubReg(SubReg1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 1834 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32);
1835 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1845 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32);
1846 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1856 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
1857 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1867 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
1868 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1879 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32);
1882 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
    [all...]
ARMISelLowering.cpp 9764 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32);
9765 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 };
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 780 SDValue RC, SubReg0, SubReg1;
785 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
789 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
794 N->getOperand(1), SubReg1 };
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 1172 unsigned SubReg1 = MI.getOperand(1).getSubReg();
1183 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
1215 MI.getOperand(2).setSubReg(SubReg1);

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