| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVExpandPseudoInsts.cpp | 297 unsigned SubRegIdx = RISCV::sub_vrm1_0;
302 SubRegIdx = RISCV::sub_vrm2_0;
307 SubRegIdx = RISCV::sub_vrm4_0;
315 .addReg(TRI->getSubReg(SrcReg, SubRegIdx + I))
342 unsigned SubRegIdx = RISCV::sub_vrm1_0;
347 SubRegIdx = RISCV::sub_vrm2_0;
352 SubRegIdx = RISCV::sub_vrm4_0;
360 TRI->getSubReg(DestReg, SubRegIdx + I))
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| RISCVISelDAGToDAG.cpp | 195 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I);
197 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg));
238 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I);
240 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg));
286 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I);
288 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg));
1058 unsigned SubRegIdx;
1059 std::tie(SubRegIdx, Idx) =
1078 // If we haven't set a SubRegIdx, then we must be going between
1080 if (SubRegIdx == RISCV::NoSubRegister)
[all...] |
| RISCVInstrInfo.cpp | 136 unsigned SubRegIdx = RISCV::sub_vrm1_0;
156 SubRegIdx = RISCV::sub_vrm1_0;
161 SubRegIdx = RISCV::sub_vrm2_0;
166 SubRegIdx = RISCV::sub_vrm4_0;
171 SubRegIdx = RISCV::sub_vrm1_0;
176 SubRegIdx = RISCV::sub_vrm2_0;
181 SubRegIdx = RISCV::sub_vrm1_0;
186 SubRegIdx = RISCV::sub_vrm2_0;
191 SubRegIdx = RISCV::sub_vrm1_0;
196 SubRegIdx = RISCV::sub_vrm1_0
[all...] |
| RISCVISelLowering.cpp | 1132 unsigned SubRegIdx = RISCV::NoSubRegister;
1139 SubRegIdx = TRI->composeSubRegIndices(SubRegIdx,
1144 return {SubRegIdx, InsertExtractIdx};
3744 unsigned SubRegIdx, RemIdx;
3745 std::tie(SubRegIdx, RemIdx) =
3893 unsigned SubRegIdx, RemIdx;
3894 std::tie(SubRegIdx, RemIdx) =
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| RenameIndependentSubregs.cpp | 182 unsigned SubRegIdx = MO.getSubReg();
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
226 unsigned SubRegIdx = MO.getSubReg();
227 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
348 unsigned SubRegIdx = MO.getSubReg();
349 if (SubRegIdx == 0)
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| RegisterPressure.cpp | 535 unsigned SubRegIdx = MO.getSubReg();
538 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses);
543 SubRegIdx = 0;
547 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs);
549 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs);
553 void pushRegLanes(Register Reg, unsigned SubRegIdx,
556 LaneBitmask LaneMask = SubRegIdx != 0
557 ? TRI.getSubRegIndexLaneMask(SubRegIdx)
1235 unsigned SubRegIdx = MO.getSubReg();
1236 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
[all...] |
| VirtRegMap.cpp | 380 unsigned SubRegIdx = MO.getSubReg();
381 assert(SubRegIdx != 0 && LI.hasSubRanges());
382 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
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| StackMaps.cpp | 251 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg());
252 if (SubRegIdx)
253 Offset = TRI->getSubRegIdxOffset(SubRegIdx);
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| RegAllocFast.cpp | 835 unsigned SubRegIdx = MO.getSubReg();
836 if (SubRegIdx != 0) {
837 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx);
|
| MachineVerifier.cpp | 2197 unsigned SubRegIdx = MO->getSubReg();
2198 LaneBitmask MOMask = SubRegIdx != 0
2199 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2295 unsigned SubRegIdx = MO->getSubReg();
2296 LaneBitmask MOMask = SubRegIdx != 0
2297 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
|
| RegisterCoalescer.cpp | 310 MachineOperand &MO, unsigned SubRegIdx);
1693 MachineOperand &MO, unsigned SubRegIdx) {
1694 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx);
1847 unsigned SubRegIdx = MO.getSubReg();
1848 if (SubRegIdx == 0 || MO.isUndef())
1851 LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86FixupBWInsts.cpp | 194 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg);
200 if (SubRegIdx == X86::sub_8bit_hi)
208 if (SubRegIdx != X86::sub_8bit)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SILoadStoreOptimizer.cpp | 1295 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired);
1296 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx);
1297 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx);
1356 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired);
1357 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx);
1358 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx);
1422 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired);
1423 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx);
1424 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx);
1453 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired)
[all...] |
| AMDGPUInstructionSelector.cpp | 1929 int SubRegIdx = sizeToSubRegIndex(DstSize);
1930 if (SubRegIdx == -1)
1936 = TRI.getSubClassWithSubReg(SrcRC, SubRegIdx);
1945 I.getOperand(1).setSubReg(SubRegIdx);
|
| AMDGPUISelDAGToDAG.cpp | 589 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
591 SubRegIdx);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEInstrInfo.cpp | 330 const unsigned *SubRegIdx,
335 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]);
336 Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]);
393 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd};
396 NumSubRegs, SubRegIdx, &getRegisterInfo());
399 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd};
402 NumSubRegs, SubRegIdx, &getRegisterInfo());
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 472 CodeGenSubRegIndex *SubRegIdx;
474 std::tie(SubRegIdx, SubReg) = SubRegQueue.front();
489 // We know that the first component is (SubRegIdx,SubReg). However we
492 assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct");
494 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) {
495 if (SubRegIdx->ConcatenationOf.empty())
496 Parts.push_back(SubRegIdx);
498 append_range(Parts, SubRegIdx->ConcatenationOf);
|
| GlobalISelEmitter.cpp | 2753 << MatchTable::Comment("SubRegIdx")
2810 const CodeGenSubRegIndex *SubRegIdx;
2819 SubRegIdx(SubReg), IsDef(IsDef), IsDead(IsDead) {}
2826 if (SubRegIdx) {
2845 if (SubRegIdx)
2846 Table << MatchTable::NamedValue(SubRegIdx->getQualifiedName());
2876 const CodeGenSubRegIndex *SubRegIdx;
2880 : OperandRenderer(OR_SubRegIndex), InsnID(InsnID), SubRegIdx(SRI) {}
2889 << MatchTable::IntValue(SubRegIdx->EnumValue)
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 890 int64_t SubRegIdx = MatchTable[CurrentIdx++];
893 0, SubRegIdx);
897 << OpIdx << ", " << SubRegIdx << ")\n");
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 1965 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
1970 SubRegIdx), 0);
1979 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
1981 MVT::i32, V, SubRegIdx), 0);
3053 SDValue SubRegIdx =
3056 ImDef, NatWidthRes, SubRegIdx), 0);
3063 SDValue SubRegIdx =
3066 NatWidthRes, SubRegIdx), 0);
5018 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_eq, dl, MVT::i32);
5022 CR6Reg, SubRegIdx, VecStrOp.getValue(1))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 249 unsigned SubRegIdx);
251 unsigned SubRegIdx);
1370 unsigned SubRegIdx) {
1384 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1399 unsigned Opc, unsigned SubRegIdx) {
1423 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/LiveDebugValues/ |
| InstrRefBasedImpl.cpp | 1831 unsigned SubRegIdx = SRI.getSubRegIndex();
1832 unsigned DstSubReg = TRI->getSubReg(DstRegNum, SubRegIdx);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 1171 unsigned SubRegIdx =
1174 Node, CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, Op).getNode());
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 3340 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0;
3397 .addReg(LaneReg, 0, SubRegIdx);
3426 .addReg(LaneTmp2, 0, SubRegIdx);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 4532 SDValue SubRegIdx =
4535 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
4545 SDValue SubRegIdx =
4548 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
|
