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    Searched refs:Subtarget (Results 1 - 25 of 187) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRuntimeLibcallSignatures.h 25 extern void getLibcallSignature(const WebAssemblySubtarget &Subtarget,
30 extern void getLibcallSignature(const WebAssemblySubtarget &Subtarget,
WebAssemblyAsmPrinter.h 22 const WebAssemblySubtarget *Subtarget;
38 : AsmPrinter(TM, std::move(Streamer)), Subtarget(nullptr), MRI(nullptr),
45 const WebAssemblySubtarget &getSubtarget() const { return *Subtarget; }
55 Subtarget = &MF.getSubtarget<WebAssemblySubtarget>();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsRegisterInfo.cpp 94 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
97 if (Subtarget.hasMips64())
98 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
101 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
105 if (Subtarget.isSingleFloat())
108 if (Subtarget.isABI_N64())
111 if (Subtarget.isABI_N32())
114 if (Subtarget.isFP64bit())
117 if (Subtarget.isFPXX())
126 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>()
    [all...]
MipsTargetMachine.h 32 const MipsSubtarget *Subtarget;
49 if (Subtarget)
50 return Subtarget;
56 /// Reset the subtarget for the Mips target.
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCLowerMASSVEntries.cpp 11 // Following is an example of a conversion specific to Power9 subtarget:
55 static StringRef getCPUSuffix(const PPCSubtarget *Subtarget);
57 const PPCSubtarget *Subtarget);
60 const PPCSubtarget *Subtarget);
72 /// Returns a string corresponding to the specified PowerPC subtarget. e.g.:
74 /// generating subtarget-specific MASSV library functions. Current support
76 StringRef PPCLowerMASSVEntries::getCPUSuffix(const PPCSubtarget *Subtarget) {
77 // Assume Power8 when Subtarget is unavailable.
78 if (!Subtarget)
80 if (Subtarget->hasP9Vector()
    [all...]
PPCRegisterInfo.cpp 158 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
160 if (!TM.isPPC64() && Subtarget.isAIXABI())
162 if (Subtarget.hasVSX()) {
163 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
167 if (Subtarget.hasAltivec()) {
168 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
183 !Subtarget.isUsingPCRelativeCalls();
187 if (Subtarget.isAIXABI())
190 if (Subtarget.hasAltivec())
197 if (Subtarget.hasAltivec()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCTargetMachine.h 25 ARCSubtarget Subtarget;
34 const ARCSubtarget *getSubtargetImpl() const { return &Subtarget; }
36 return &Subtarget;
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFTargetMachine.h 22 BPFSubtarget Subtarget;
30 const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; }
32 return &Subtarget;
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreTargetMachine.h 28 XCoreSubtarget Subtarget;
37 const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; }
39 return &Subtarget;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86LoadValueInjectionRetHardening.cpp 63 const X86Subtarget *Subtarget = &MF.getSubtarget<X86Subtarget>();
64 if (!Subtarget->useLVIControlFlowIntegrity() || !Subtarget->is64Bit())
73 const X86RegisterInfo *TRI = Subtarget->getRegisterInfo();
74 const X86InstrInfo *TII = Subtarget->getInstrInfo();
X86SelectionDAGInfo.cpp 52 const X86Subtarget &Subtarget =
70 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) {
121 if (Subtarget.is64Bit() && Alignment > Align(8)) { // QWORD aligned
154 bool Use64BitRegs = Subtarget.isTarget64BitLP64();
185 static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG,
188 const bool Use64BitRegs = Subtarget.isTarget64BitLP64();
207 static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG,
210 return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src,
215 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget,
227 return Subtarget.is64Bit() ? MVT::i64 : MVT::i32
    [all...]
X86LegalizerInfo.h 29 const X86Subtarget &Subtarget;
X86SpeculativeExecutionSideEffectSuppression.cpp 92 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
98 !(Subtarget.useLVILoadHardening() && OptLevel == CodeGenOpt::None) &&
99 !Subtarget.useSpeculativeExecutionSideEffectSuppression())
105 const X86InstrInfo *TII = Subtarget.getInstrInfo();
X86ISelLowering.cpp 115 : TargetLowering(TM), Subtarget(STI) {
116 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
117 X86ScalarSSEf64 = Subtarget.hasSSE2();
118 X86ScalarSSEf32 = Subtarget.hasSSE1();
131 if (Subtarget.isAtom())
133 else if (Subtarget.is64Bit())
137 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
142 if (Subtarget.hasSlowDivide32())
144 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiFrameLowering.h 32 explicit LanaiFrameLowering(const LanaiSubtarget &Subtarget)
36 STI(Subtarget) {}
LanaiTargetMachine.h 25 LanaiSubtarget Subtarget;
38 return &Subtarget;
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kTargetMachine.h 31 M68kSubtarget Subtarget;
43 const M68kSubtarget *getSubtargetImpl() const { return &Subtarget; }
M68kAsmPrinter.h 44 const M68kSubtarget *Subtarget;
51 Subtarget = static_cast<M68kTargetMachine &>(TM).getSubtargetImpl();
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430TargetMachine.h 27 MSP430Subtarget Subtarget;
37 return &Subtarget;
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVInstructionSelector.cpp 49 // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
51 // Subtarget variable.
52 const RISCVSubtarget *Subtarget = &STI;
100 RISCVSubtarget &Subtarget,
102 return new RISCVInstructionSelector(TM, Subtarget, RBI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VETargetMachine.h 24 VESubtarget Subtarget;
36 const VESubtarget *getSubtargetImpl() const { return &Subtarget; }
38 return &Subtarget;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
LeonPasses.cpp 40 Subtarget = &MF.getSubtarget<SparcSubtarget>();
41 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
77 Subtarget = &MF.getSubtarget<SparcSubtarget>();
127 Subtarget = &MF.getSubtarget<SparcSubtarget>();
128 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
SparcRegisterInfo.cpp 56 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
67 if (!Subtarget.is64Bit())
82 if (ReserveAppRegisters || !Subtarget.is64Bit())
90 if (!Subtarget.isV9()) {
107 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
108 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
173 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
182 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
184 const TargetInstrInfo &TII = *Subtarget.getInstrInfo()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXTargetMachine.h 30 NVPTXSubtarget Subtarget;
43 return &Subtarget;
45 const NVPTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonAsmPrinter.h 30 const HexagonSubtarget *Subtarget = nullptr;
38 Subtarget = &Fn.getSubtarget<HexagonSubtarget>();

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