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    Searched refs:SuperRC (Results 1 - 16 of 16) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
AggressiveAntiDepBreaker.cpp 621 const TargetRegisterClass *SuperRC =
624 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
632 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
634 unsigned OrigR = RenameOrder[SuperRC];
728 RenameOrder.erase(SuperRC);
729 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
MachineCopyPropagation.cpp 436 const TargetRegisterClass *SuperRC = UseDstRC;
438 SuperRC; SuperRC = *SuperRCI++)
439 if (SuperRC->contains(CopySrcReg))
RegAllocGreedy.cpp 2070 /// on \p MI and that are also in \p SuperRC.
2072 const MachineInstr *MI, Register Reg, const TargetRegisterClass *SuperRC,
2075 assert(SuperRC && "Invalid register class");
2078 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI,
2112 const TargetRegisterClass *SuperRC =
2114 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
2123 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC,
TargetLoweringBase.cpp 1245 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1247 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1249 if (!isLegalRC(*TRI, *SuperRC))
1251 BestRC = SuperRC;
MachineVerifier.cpp 2010 const TargetRegisterClass *SuperRC =
2012 if (!SuperRC) {
2016 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 1078 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired);
1079 Register DestReg = MRI->createVirtualRegister(SuperRC);
1221 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired);
1223 Register DestReg = MRI->createVirtualRegister(SuperRC);
1275 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired);
1277 Register DestReg = MRI->createVirtualRegister(SuperRC);
1326 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired);
1329 Register DestReg = MRI->createVirtualRegister(SuperRC);
1387 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired);
1390 Register DestReg = MRI->createVirtualRegister(SuperRC);
    [all...]
SIRegisterInfo.h 199 /// Returns a register class which is compatible with \p SuperRC, such that a
204 getCompatibleSubRegClass(const TargetRegisterClass *SuperRC,
SIInstrInfo.h 65 const TargetRegisterClass *SuperRC,
71 const TargetRegisterClass *SuperRC,
SIRegisterInfo.cpp 2153 SIRegisterInfo::getCompatibleSubRegClass(const TargetRegisterClass *SuperRC,
2158 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx);
2159 return MatchRC && MatchRC->hasSubClassEq(SuperRC) ? MatchRC : nullptr;
SIInstrInfo.cpp 4532 const TargetRegisterClass *SuperRC,
4550 Register NewSuperReg = MRI.createVirtualRegister(SuperRC);
4565 const TargetRegisterClass *SuperRC,
4577 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
4606 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF);
4607 if (!SuperRC)
4610 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg());
AMDGPUISelDAGToDAG.cpp 585 const TargetRegisterClass *SuperRC =
590 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
AMDGPUInstructionSelector.cpp 2588 const TargetRegisterClass *SuperRC,
2602 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize);
SIISelLowering.cpp 3635 const TargetRegisterClass *SuperRC,
3638 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonRegisterInfo.cpp 438 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
439 return getHexagonSubRegIndex(*SuperRC, GenIdx);
HexagonCopyToCombine.cpp 594 const TargetRegisterClass *SuperRC = nullptr;
596 SuperRC = &Hexagon::DoubleRegsRegClass;
600 SuperRC = &Hexagon::HvxWRRegClass;
606 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC);
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.h 315 // classes SuperRC such that:
317 // R:SubRegIndex in this RC for all R in SuperRC.
412 CodeGenRegisterClass *SuperRC) {
413 SuperRegClasses[SubIdx].insert(SuperRC);

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