| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZCallingConv.cpp | 1 //===-- SystemZCallingConv.cpp - Calling conventions for SystemZ ----------===//
14 const MCPhysReg SystemZ::ELFArgGPRs[SystemZ::ELFNumArgGPRs] = {
15 SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D
18 const MCPhysReg SystemZ::ELFArgFPRs[SystemZ::ELFNumArgFPRs] =
[all...] |
| SystemZInstrInfo.cpp | 1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
15 #include "SystemZ.h"
48 #define DEBUG_TYPE "systemz-II"
59 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
81 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
82 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
125 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
141 bool IsHigh = SystemZ::isHighReg(Reg)
[all...] |
| SystemZShortenInst.cpp | 23 #define DEBUG_TYPE "systemz-shorten-inst"
32 return "SystemZ Instruction Shortening";
82 (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32
83 : SystemZ::subreg_l32);
85 (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32
86 : SystemZ::subreg_l32);
88 TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);
94 if (SystemZ::isImmLL(Imm))
[all...] |
| SystemZAsmPrinter.cpp | 1 //===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//
9 // Streams SystemZ assembly language and associated data, in the form of
132 case SystemZ::Return:
135 MCInstBuilder(SystemZ::B).addReg(SystemZ::R7D).addImm(2).addReg(0);
137 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D);
140 case SystemZ::CondReturn:
141 LoweredMI = MCInstBuilder(SystemZ::BCR)
144 .addReg(SystemZ::R14D)
[all...] |
| SystemZLongBranch.cpp | 1 //===-- SystemZLongBranch.cpp - Branch lengthening for SystemZ ------------===//
34 // On SystemZ, long branches are only needed for functions bigger than 64k,
55 #include "SystemZ.h"
73 #define DEBUG_TYPE "systemz-long-branch"
141 StringRef getPassName() const override { return "SystemZ Long Branch"; }
218 case SystemZ::J:
222 case SystemZ::BRC:
226 case SystemZ::BRCT:
227 case SystemZ::BRCTG:
231 case SystemZ::BRCTH
[all...] |
| SystemZElimCompare.cpp | 15 #include "SystemZ.h"
36 #define DEBUG_TYPE "systemz-elim-compare"
72 return "SystemZ Comparison Elimination";
112 case SystemZ::LR:
113 case SystemZ::LGR:
114 case SystemZ::LGFR:
115 case SystemZ::LTR:
116 case SystemZ::LTGR:
117 case SystemZ::LTGFR:
118 case SystemZ::LER
[all...] |
| SystemZFrameLowering.cpp | 1 //===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
28 { SystemZ::R2D, 0x10 },
29 { SystemZ::R3D, 0x18 },
30 { SystemZ::R4D, 0x20 },
31 { SystemZ::R5D, 0x28 },
32 { SystemZ::R6D, 0x30 },
33 { SystemZ::R7D, 0x38 },
34 { SystemZ::R8D, 0x40 },
35 { SystemZ::R9D, 0x48 },
36 { SystemZ::R10D, 0x50 }
[all...] |
| SystemZTDC.cpp | 46 #include "SystemZ.h"
123 INITIALIZE_PASS(SystemZTDCPass, "systemz-tdc",
124 "SystemZ Test Data Class optimization", false, false)
169 SystemZ::TDCMASK_ZERO, // eq
170 SystemZ::TDCMASK_POSITIVE, // gt
171 SystemZ::TDCMASK_NEGATIVE, // lt
172 SystemZ::TDCMASK_NAN, // un
175 SystemZ::TDCMASK_INFINITY_PLUS, // eq
177 (SystemZ::TDCMASK_ZERO |
178 SystemZ::TDCMASK_NEGATIVE
[all...] |
| SystemZRegisterInfo.h | 1 //===-- SystemZRegisterInfo.h - SystemZ register information ----*- C++ -*-===//
12 #include "SystemZ.h"
22 namespace SystemZ {
35 if (SystemZ::GRH32BitRegClass.contains(Reg))
37 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
40 } // end namespace SystemZ
42 /// A SystemZ-specific class detailing special use registers
78 return SystemZ::R7D;
81 int getStackPointerRegister() override final { return SystemZ::R4D; };
83 int getFramePointerRegister() override final { return SystemZ::R8D; }
[all...] |
| SystemZCopyPhysRegs.cpp | 28 #define SYSTEMZ_COPYPHYSREGS_NAME "SystemZ Copy Physregs"
61 INITIALIZE_PASS(SystemZCopyPhysRegs, "systemz-copy-physregs",
89 (SrcReg == SystemZ::CC || SystemZ::AR32BitRegClass.contains(SrcReg))) {
90 Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass);
91 if (SrcReg == SystemZ::CC)
92 BuildMI(MBB, MI, DL, TII->get(SystemZ::IPM), Tmp);
94 BuildMI(MBB, MI, DL, TII->get(SystemZ::EAR), Tmp).addReg(SrcReg);
99 SystemZ::AR32BitRegClass.contains(DstReg)) {
100 Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass)
[all...] |
| SystemZMachineFunctionInfo.h | 1 //=== SystemZMachineFunctionInfo.h - SystemZ machine function info -*- C++ -*-//
16 namespace SystemZ {
30 SystemZ::GPRRegs SpillGPRRegs;
31 SystemZ::GPRRegs RestoreGPRRegs;
49 SystemZ::GPRRegs getSpillGPRRegs() const { return SpillGPRRegs; }
59 SystemZ::GPRRegs getRestoreGPRRegs() const { return RestoreGPRRegs; }
|
| SystemZRegisterInfo.cpp | 1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
32 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
33 MO.getSubReg() == SystemZ::subreg_l32 ||
34 MO.getSubReg() == SystemZ::subreg_hl32)
35 return &SystemZ::GR32BitRegClass;
36 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
37 MO.getSubReg() == SystemZ::subreg_h32 ||
38 MO.getSubReg() == SystemZ::subreg_hh32)
39 return &SystemZ::GRH32BitRegClass;
43 if (SystemZ::GR32BitRegClass.contains(PhysReg)
[all...] |
| SystemZPostRewrite.cpp | 16 #include "SystemZ.h"
24 #define SYSTEMZ_POSTREWRITE_NAME "SystemZ Post Rewrite pass"
26 #define DEBUG_TYPE "systemz-postrewrite"
72 INITIALIZE_PASS(SystemZPostRewrite, "systemz-post-rewrite",
91 bool DestIsHigh = SystemZ::isHighReg(DestReg);
92 bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
113 bool DestIsHigh = SystemZ::isHighReg(DestReg);
114 bool Src1IsHigh = SystemZ::isHighReg(Src1Reg);
115 bool Src2IsHigh = SystemZ::isHighReg(Src2Reg);
123 TII->get(SystemZ::COPY), DestReg
[all...] |
| SystemZCallingConv.h | 1 //===-- SystemZCallingConv.h - Calling conventions for SystemZ --*- C++ -*-===//
18 namespace SystemZ {
30 } // end namespace SystemZ
121 Reg = State.AllocateReg(SystemZ::ELFArgGPRs);
123 Reg = State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
147 State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
151 State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
152 State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
157 for (unsigned I = 0; I < SystemZ::XPLINK64NumArgFPRs; I += 2)
158 if (State.isAllocated(SystemZ::XPLINK64ArgFPRs[I])
[all...] |
| SystemZISelLowering.cpp | 1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
31 #define DEBUG_TYPE "systemz-lower"
87 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
89 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
90 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
93 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
94 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
96 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
97 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
100 addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass)
[all...] |
| SystemZLDCleanup.cpp | 36 return "SystemZ Local Dynamic TLS Access Clean-up";
95 case SystemZ::TLS_LDCALL:
120 TII->get(TargetOpcode::COPY), SystemZ::R2D)
135 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&SystemZ::GR64BitRegClass);
141 .addReg(SystemZ::R2D);
|
| SystemZISelDAGToDAG.cpp | 1 //===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===//
9 // This file defines an instruction selector for the SystemZ target.
23 #define DEBUG_TYPE "systemz-isel"
367 return "SystemZ DAG->DAG Pattern Instruction Selection";
781 if (RxSBG.Opcode == SystemZ::RNSBG)
791 if (RxSBG.Opcode == SystemZ::RNSBG)
814 if (RxSBG.Opcode != SystemZ::RNSBG)
855 if (RxSBG.Opcode != SystemZ::RNSBG) {
894 if (RxSBG.Opcode == SystemZ::RNSBG) {
921 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCTargetDesc.cpp | 1 //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
32 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
33 SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
34 SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L
[all...] |
| SystemZMCObjectWriter.cpp | 1 //===-- SystemZMCObjectWriter.cpp - SystemZ ELF writer --------------------===//
59 case SystemZ::FK_390_PC12DBL: return ELF::R_390_PC12DBL;
60 case SystemZ::FK_390_PC16DBL: return ELF::R_390_PC16DBL;
61 case SystemZ::FK_390_PC24DBL: return ELF::R_390_PC24DBL;
62 case SystemZ::FK_390_PC32DBL: return ELF::R_390_PC32DBL;
90 case SystemZ::FK_390_TLS_CALL: return ELF::R_390_TLS_LDCALL;
100 case SystemZ::FK_390_TLS_CALL: return ELF::R_390_TLS_GDCALL;
108 case SystemZ::FK_390_PC12DBL: return ELF::R_390_PLT12DBL;
109 case SystemZ::FK_390_PC16DBL: return ELF::R_390_PLT16DBL;
110 case SystemZ::FK_390_PC24DBL: return ELF::R_390_PLT24DBL
[all...] |
| SystemZMCFixups.h | 1 //===-- SystemZMCFixups.h - SystemZ-specific fixup entries ------*- C++ -*-===//
15 namespace SystemZ {
28 } // end namespace SystemZ
|
| SystemZMCAsmBackend.cpp | 1 //===-- SystemZMCAsmBackend.cpp - SystemZ assembler backend ---------------===//
28 case SystemZ::FK_390_PC12DBL:
29 case SystemZ::FK_390_PC16DBL:
30 case SystemZ::FK_390_PC24DBL:
31 case SystemZ::FK_390_PC32DBL:
34 case SystemZ::FK_390_TLS_CALL:
50 return SystemZ::NumTargetFixupKinds;
72 const static MCFixupKindInfo Infos[SystemZ::NumTargetFixupKinds] = {
|
| SystemZMCCodeEmitter.cpp | 1 //===-- SystemZMCCodeEmitter.cpp - Convert SystemZ code to machine code ---===//
106 SystemZ::FK_390_PC16DBL, 2, false);
112 SystemZ::FK_390_PC32DBL, 2, false);
118 SystemZ::FK_390_PC16DBL, 2, true);
124 SystemZ::FK_390_PC32DBL, 2, true);
130 SystemZ::FK_390_PC12DBL, 1, false);
136 SystemZ::FK_390_PC16DBL, 4, false);
142 SystemZ::FK_390_PC24DBL, 3, false);
295 (MCFixupKind)SystemZ::FK_390_TLS_CALL));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
626 { "e", SystemZ::InsnE, 1,
628 { "ri", SystemZ::InsnRI, 3,
630 { "rie", SystemZ::InsnRIE, 4,
632 { "ril", SystemZ::InsnRIL, 3,
634 { "rilu", SystemZ::InsnRILU, 3,
636 { "ris", SystemZ::InsnRIS, 5,
638 { "rr", SystemZ::InsnRR, 3,
640 { "rre", SystemZ::InsnRRE, 3,
642 { "rrf", SystemZ::InsnRRF, 5
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/Basic/Targets/ |
| SystemZ.cpp | 1 //===--- SystemZ.cpp - Implement SystemZ target feature support -----------===//
9 // This file implements SystemZ TargetInfo objects.
13 #include "SystemZ.h"
116 .Case("systemz", true)
151 return llvm::makeArrayRef(BuiltinInfo, clang::SystemZ::LastTSBuiltin -
|
| /src/external/apache2/llvm/lib/libclangBasic/ |
| Makefile | 68 SystemZ.cpp \
|
