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    Searched refs:TCSR_DIV_256 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/evbmips/ingenic/
machdep.c	350 writereg(JZ_WDOG_TCSR, TCSR_RTC_EN | TCSR_DIV_256);
/src/sys/arch/mips/ingenic/
ingenic_regs.h	60 #define TCSR_DIV_256 0x20

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