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    Searched refs:TEGRA186_CLK_EQOS_AXI (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
tegra186-clock.h	272 * @def TEGRA186_CLK_EQOS_AXI 598 #define TEGRA186_CLK_EQOS_AXI 167 799 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/nvidia/
tegra186.dtsi	56 <&bpmp TEGRA186_CLK_EQOS_AXI>,

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