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    Searched refs:TEGRA186_CLK_PLLC4_VCO (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
tegra186-clock.h 214 * @def TEGRA186_CLK_PLLC4_VCO
761 /** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
763 /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
765 /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
855 #define TEGRA186_CLK_PLLC4_VCO 524
870 /** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/nvidia/
tegra186.dtsi 718 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
719 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;

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