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    Searched refs:TESR_TCST5 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/evbmips/ingenic/
clock.c	99 writereg(JZ_TC_TECR, TESR_TCST5); /* disable timer 5 */ 106 writereg(JZ_TC_TESR, TESR_TCST5); /* enable timer 5 */
/src/sys/arch/mips/ingenic/
ingenic_regs.h	71 #define TESR_TCST5 0x0020 /* enable counter 5 */

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