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Searched refs:THM_CLK_CNTL__CMON_CLK_SEL__SHIFT (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_ci_baco.c	`124 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x2 },`
amdgpu_fiji_baco.c	`108 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },`
amdgpu_polaris_baco.c	`103 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },`
amdgpu_tonga_baco.c	`116 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik.c	`1757 data \|= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) \|`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_7_0_0_sh_mask.h	`266 #define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0`
smu_7_1_1_sh_mask.h	`264 #define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0`
smu_7_0_1_sh_mask.h	`264 #define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0`
smu_7_1_0_sh_mask.h	`262 #define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0`
smu_7_1_2_sh_mask.h	`264 #define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0`
smu_7_1_3_sh_mask.h	`292 #define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0`

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