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Searched refs:THM_CLK_CNTL__TMON_CLK_SEL_MASK (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_ci_baco.c	`125 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x2 }`
amdgpu_fiji_baco.c	`109 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 }`
amdgpu_polaris_baco.c	`104 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 },`
amdgpu_tonga_baco.c	`117 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 }`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik.c	`1756 THM_CLK_CNTL__TMON_CLK_SEL_MASK);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_7_0_0_sh_mask.h	`267 #define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00`
smu_7_1_1_sh_mask.h	`265 #define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00`
smu_7_0_1_sh_mask.h	`265 #define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00`
smu_7_1_0_sh_mask.h	`263 #define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00`
smu_7_1_2_sh_mask.h	`265 #define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00`
smu_7_1_3_sh_mask.h	`293 #define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00`

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