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Searched refs:THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/thm/
thm_11_0_2_sh_mask.h	`49 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4`
thm_10_0_sh_mask.h	`130 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4`
thm_9_0_sh_mask.h	`274 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4`
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega12_thermal.c	`217 val \|= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);`
amdgpu_vega20_thermal.c	`287 val \|= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);`
amdgpu_vega10_thermal.c	`449 val \|= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);`
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_smu_v11_0.c	`1194 val \|= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_8_0_sh_mask.h	`152 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4`

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