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    Searched refs:TIED_TO (Results 1 - 23 of 23) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCInstrDesc.h 34 TIED_TO = 0, // Must be allocated the same register as specified value.
40 ((1 << MCOI::TIED_TO) | ((op) << (4 + MCOI::TIED_TO * 4)))
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86BaseInfo.h 1055 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
1057 // Check for AVX-512 scatter which has a TIED_TO in the second to last
1060 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0)
1065 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
1066 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
1070 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
1071 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 ||
1072 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1))
X86InstComments.cpp 271 if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1)
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZHazardRecognizer.cpp 127 MID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
SystemZShortenInst.cpp 68 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 &&
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
MCInstrDescView.cpp 121 int TiedToIndex = Description->getOperandConstraint(OpIndex, MCOI::TIED_TO);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.cpp 214 if (MCID.getOperandConstraint(I, MCOI::TIED_TO) != -1)
454 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
ScheduleDAGRRList.cpp 1036 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
2826 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) {
3071 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1)
ScheduleDAGFast.cpp 256 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
InstrEmitter.cpp 358 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/
M68kDisassembler.cpp 557 int TiedTo = Desc.getOperandConstraint(DstMIOpIdx, MCOI::TIED_TO);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetInstrInfo.cpp 207 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
212 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
MachineInstr.cpp 289 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
1507 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
MachineVerifier.cpp 1821 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
1865 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
Utils.cpp 172 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 617 MCOI::OperandConstraint::TIED_TO);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrInfo.cpp 2643 MCOI::TIED_TO) != -1)) {
5526 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5636 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5638 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 7437 && Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1;
7962 MCOI::TIED_TO);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 4161 (MCID.getOperandConstraint(i, MCOI::TIED_TO) == -1) &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 1181 assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp 860 VCCPos + 2, MCOI::TIED_TO);
6220 // later, and will infer the register number from the TIED_TO
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 2496 int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 11701 int DefIdx = MCID->getOperandConstraint(i, MCOI::TIED_TO);

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