| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUMIRFormatter.cpp | 24 const SIInstrInfo &TII = *MF.getSubtarget<GCNSubtarget>().getInstrInfo();
26 PSV = MFI->getBufferPSV(TII);
30 PSV = MFI->getImagePSV(TII);
34 PSV = MFI->getGWSPSV(TII);
|
| R600ExpandSpecialInstrs.cpp | 29 const R600InstrInfo *TII = nullptr;
63 int OpIdx = TII->getOperandIdx(*OldMI, Op);
66 TII->setImmOperand(*NewMI, Op, Val);
72 TII = ST.getInstrInfo();
74 const R600RegisterInfo &TRI = TII->getRegisterInfo();
85 if (TII->isLDSRetInstr(MI.getOpcode())) {
86 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
89 MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
92 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(),
94 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode()
[all...] |
| SIPeepholeSDWA.cpp | 49 const SIInstrInfo *TII;
95 virtual MachineInstr *potentialToConvert(const SIInstrInfo *TII) = 0;
96 virtual bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) = 0;
128 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override;
129 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
136 uint64_t getSrcMods(const SIInstrInfo *TII,
155 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override;
156 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
176 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
304 uint64_t SDWASrcOperand::getSrcMods(const SIInstrInfo *TII,
[all...] |
| R600EmitClauseMarkers.cpp | 33 const R600InstrInfo *TII = nullptr;
51 if (TII->isLDSRetInstr(MI.getOpcode()))
54 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()) ||
55 TII->isReductionOp(MI.getOpcode()))
70 if (TII->isALUInstr(MI.getOpcode()))
72 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()))
118 if (!TII->isALUInstr(MI.getOpcode()) && MI.getOpcode() != R600::DOT_4)
122 TII->getSrcs(MI)
[all...] |
| SIShrinkInstructions.cpp | 62 static bool foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
64 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI));
78 if (TII->isOperandLegal(MI, Src0Idx, &MovSrc)) {
105 if (TII->commuteInstruction(MI)) {
106 if (foldImmediates(MI, TII, MRI, false))
110 TII->commuteInstruction(MI);
117 static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) {
119 !TII->isInlineConstant(*Src.getParent()
[all...] |
| R600Packetizer.cpp | 52 const R600InstrInfo *TII;
67 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
79 if (TII->isPredicated(*BI))
81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write);
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst);
89 if (isTrans || TII->isTransOnly(*BI)) {
131 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]);
145 TII(ST.getInstrInfo()),
146 TRI(TII->getRegisterInfo()) {
164 if (TII->isVector(MI)
[all...] |
| R600ClauseMergePass.cpp | 38 const R600InstrInfo *TII;
78 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT))
85 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled))
91 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT);
110 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT);
114 if (CumuledInsts >= TII->getMaxAlusPerClause()) {
122 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0);
124 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0);
126 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0);
138 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1)
[all...] |
| GCNDPPCombine.cpp | 56 const SIInstrInfo *TII;
119 if (!TII->isVOP3(Op)) {
122 if (!TII->hasVALU32BitEncoding(Op)) {
126 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) {
152 return (DPP32 == -1 || TII->pseudoToMCOpcode(DPP32) == -1) ? -1 : DPP32;
196 OrigMI.getDebugLoc(), TII->get(DPPOp))
201 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst);
212 TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()),
226 if (auto *Mod0 = TII->getNamedOperand(OrigMI,
238 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0)
[all...] |
| SIModeRegister.cpp | 137 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
139 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
141 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
143 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
146 const SIInstrInfo *TII, Status InstrMode);
164 const SIInstrInfo *TII) {
165 if (TII->usesFPDPRounding(MI)) {
186 const SIInstrInfo *TII, Status InstrMode) {
191 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32))
222 const SIInstrInfo *TII) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kExpandPseudo.cpp | 47 const M68kInstrInfo *TII;
85 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8);
87 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8);
89 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16);
92 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8);
94 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8);
96 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16);
99 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8);
101 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i8);
103 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i16)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyLowerBrUnless.cpp | 62 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
81 Def->setDesc(TII.get(NE_I32));
85 Def->setDesc(TII.get(EQ_I32));
89 Def->setDesc(TII.get(LE_S_I32));
93 Def->setDesc(TII.get(LT_S_I32));
97 Def->setDesc(TII.get(GE_S_I32));
101 Def->setDesc(TII.get(GT_S_I32));
105 Def->setDesc(TII.get(LE_U_I32));
109 Def->setDesc(TII.get(LT_U_I32));
113 Def->setDesc(TII.get(GE_U_I32))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| PseudoSourceValue.cpp | 27 PseudoSourceValue::PseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII)
29 AddressSpace = TII.getAddressSpaceForPseudoSourceKind(Kind);
83 unsigned Kind, const TargetInstrInfo &TII)
84 : PseudoSourceValue(Kind, TII) {}
100 const TargetInstrInfo &TII)
101 : CallEntryPseudoSourceValue(GlobalValueCallEntry, TII), GV(GV) {}
103 const char *ES, const TargetInstrInfo &TII)
104 : CallEntryPseudoSourceValue(ExternalSymbolCallEntry, TII), ES(ES) {}
108 : TII(TIInfo),
109 StackPSV(PseudoSourceValue::Stack, TII),
[all...] |
| PostRAHazardRecognizer.cpp | 70 const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
72 TII->CreateTargetPostRAHazardRecognizer(Fn));
86 TII->insertNoops(MBB, MachineBasicBlock::iterator(MI), NumPreNoops);
|
| FEntryInserter.cpp | 44 auto *TII = MF.getSubtarget().getInstrInfo();
46 TII->get(TargetOpcode::FENTRY_CALL));
|
| XRayInstrumentation.cpp | 70 const TargetInstrInfo *TII,
82 const TargetInstrInfo *TII,
89 MachineFunction &MF, const TargetInstrInfo *TII,
98 (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) {
103 if (TII->isTailCall(T) && op.HandleTailcall) {
109 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc))
125 MachineFunction &MF, const TargetInstrInfo *TII,
131 (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) {
134 if (TII->isTailCall(T) && op.HandleTailcall) {
140 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64A53Fix835769.cpp | 80 const TargetInstrInfo *TII;
120 TII = F.getSubtarget().getInstrInfo();
131 const TargetInstrInfo *TII) {
144 if (S == PrevBB && !TII->analyzeBranch(*PrevBB, TBB, FBB, Cond) && !TBB &&
156 const TargetInstrInfo *TII) {
161 while ((FMBB = getBBFallenThrough(FMBB, TII))) {
172 const TargetInstrInfo *TII) {
176 MachineInstr *I = getLastNonPseudo(MBB, TII);
179 BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0);
183 BuildMI(MBB, MI, DL, TII->get(AArch64::HINT)).addImm(0)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86LoadValueInjectionRetHardening.cpp | 74 const X86InstrInfo *TII = Subtarget->getInstrInfo();
84 BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::POP64r))
87 BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::LFENCE));
88 BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::JMP64r))
97 BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::LFENCE));
98 addRegOffset(BuildMI(MBB, Fence, DebugLoc(), TII->get(X86::SHL64mi)),
|
| X86LowerTileCopy.cpp | 74 const X86InstrInfo *TII = ST.getInstrInfo();
106 BuildMI(MBB, MI, DL, TII->get(X86::IMPLICIT_DEF), GR64Cand);
107 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64mr)), StrideSS)
110 BuildMI(MBB, MI, DL, TII->get(X86::MOV64ri), GR64Cand).addImm(64);
114 addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc)), TileSS)
121 NewMI = addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc), DstReg),
125 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm), GR64Cand),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 45 const MSP430InstrInfo &TII =
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::R4)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP)
110 const MSP430InstrInfo &TII =
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::R4);
157 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::R4);
161 TII.get(MSP430::SUB16ri), MSP430::SP)
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP)
189 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonHazardRecognizer.cpp | 41 if (!MI || TII->isZeroCost(MI->getOpcode()))
47 if (TII->mayBeNewStore(*MI)) {
57 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
119 if (TII->isZeroCost(MI->getOpcode()))
125 assert(TII->mayBeNewStore(*MI) && "Expecting .new store");
128 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
142 if (TII->mayBeCurLoad(*MI))
157 if (TII->isHVXVec(*MI) && !MI->mayLoad() && !MI->mayStore()
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineLoopUtils.h | 38 const TargetInstrInfo *TII);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| Mips16FrameLowering.cpp | 45 const Mips16InstrInfo &TII =
62 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
67 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
82 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
87 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
95 const Mips16InstrInfo &TII =
104 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
109 TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI);
163 const Mips16InstrInfo &TII =
165 const MipsRegisterInfo &RI = TII.getRegisterInfo()
[all...] |
| MipsInstructionSelector.cpp | 61 const MipsInstrInfo &TII;
83 : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
113 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
261 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
266 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEFrameLowering.cpp | 142 const VEInstrInfo &TII = *STI.getInstrInfo();
152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
176 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
190 const VEInstrInfo &TII = *STI.getInstrInfo();
200 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17)
205 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16)
209 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRFrameLowering.cpp | 57 const AVRInstrInfo &TII = *STI.getInstrInfo();
63 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
75 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0)
78 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
81 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
104 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28)
121 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
129 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
141 const AVRInstrInfo &TII = *STI.getInstrInfo()
[all...] |
