| /src/sys/external/bsd/sljit/dist/sljit_src/ |
| sljitNativeSPARC_32.c | 50 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
57 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
70 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
80 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
84 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
87 FAIL_IF(push_inst(compiler, OR | D(TMP_REG1) | S1(0) | S2(src2), DR(TMP_REG1)));
93 FAIL_IF(push_inst(compiler, SUB | SET_FLAGS | D(0) | S1(TMP_REG1) | S2(0), SET_FLAGS));
94 FAIL_IF(push_inst(compiler, SLL | D(TMP_REG1) | S1(TMP_REG1) | IMM(1), DR(TMP_REG1)))
[all...] |
| sljitNativeX86_common.c | 69 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2)
88 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2)
648 inst = emit_x86_instruction(compiler, 1, TMP_REG1, 0, src, srcw);
695 inst = emit_x86_instruction(compiler, 1, TMP_REG1, 0, src, srcw);
698 inst = emit_x86_instruction(compiler, 1, TMP_REG1, 0, dst, dstw);
738 && reg_map[TMP_REG1] > 7);
743 && reg_map[TMP_REG1] == 2);
752 EMIT_MOV(compiler, TMP_REG1, 0, SLJIT_R1, 0);
755 inst = emit_x86_instruction(compiler, 1, TMP_REG1, 0, TMP_REG1, 0)
[all...] |
| sljitNativeARM_64.c | 39 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2)
529 /* dst must be register, TMP_REG1
530 arg1 must be register, TMP_REG1, imm
544 FAIL_IF(load_immediate(compiler, TMP_REG1, arg1));
545 arg1 = TMP_REG1;
563 SLJIT_ASSERT(!(flags & SET_FLAGS) && (flags & ARG2_IMM) && arg1 == TMP_REG1);
666 FAIL_IF(load_immediate(compiler, TMP_REG1, arg1));
667 arg1 = TMP_REG1;
678 SLJIT_ASSERT(!(flags & SET_FLAGS) && arg1 == TMP_REG1);
684 SLJIT_ASSERT(!(flags & SET_FLAGS) && arg1 == TMP_REG1);
[all...] |
| sljitNativeMIPS_common.c | 49 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2)
568 FAIL_IF(load_immediate(compiler, DR(TMP_REG1), local_size));
570 FAIL_IF(push_inst(compiler, SUBU_W | S(SLJIT_SP) | T(TMP_REG1) | D(SLJIT_SP), DR(SLJIT_SP)));
630 FAIL_IF(load_immediate(compiler, DR(TMP_REG1), local_size));
631 FAIL_IF(push_inst(compiler, ADDU_W | S(SLJIT_SP) | T(TMP_REG1) | D(TMP_REG1), DR(TMP_REG1)));
632 base = S(TMP_REG1);
657 return push_inst(compiler, ADDU_W | S(TMP_REG1) | TA(0) | D(SLJIT_SP), UNMOVABLE_INS);
758 tmp_ar = DR(TMP_REG1);
[all...] |
| sljitNativeARM_T2_32.c | 38 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2)
520 /* dst must be register, TMP_REG1
529 FAIL_IF(load_immediate(compiler, TMP_REG1, arg1));
530 arg1 = TMP_REG1;
676 arg2 = (arg1 == TMP_REG1) ? TMP_REG2 : TMP_REG1;
681 arg1 = (arg2 == TMP_REG1) ? TMP_REG2 : TMP_REG1;
1235 dst_r = SLOW_IS_REG(dst) ? dst : TMP_REG1;
1301 FAIL_IF(emit_op_mem(compiler, flags, dst_r, src, srcw, ((flags & UPDATE) && dst_r == TMP_REG1) ? TMP_REG2 : TMP_REG1))
[all...] |
| sljitNativeMIPS_64.c | 171 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
178 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
193 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
212 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
216 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
224 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
236 FAIL_IF(push_inst(compiler, SELECT_OP(DADDU, ADDU) | S(src2) | TA(0) | D(TMP_REG1), DR(TMP_REG1)));
238 FAIL_IF(push_inst(compiler, BEQ | S(TMP_REG1) | TA(0) | IMM(5), UNMOVABLE_INS));
243 FAIL_IF(push_inst(compiler, BGEZ | S(TMP_REG1) | IMM(-2), UNMOVABLE_INS))
[all...] |
| sljitNativeMIPS_32.c | 81 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
88 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
107 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
125 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
133 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
145 FAIL_IF(push_inst(compiler, ADDU | S(src2) | TA(0) | D(TMP_REG1), DR(TMP_REG1)));
147 FAIL_IF(push_inst(compiler, BEQ | S(TMP_REG1) | TA(0) | IMM(5), UNMOVABLE_INS));
152 FAIL_IF(push_inst(compiler, BGEZ | S(TMP_REG1) | IMM(-2), UNMOVABLE_INS));
153 FAIL_IF(push_inst(compiler, SLL | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(1), UNMOVABLE_INS))
[all...] |
| sljitNativeSPARC_common.c | 92 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2)
453 FAIL_IF(load_immediate(compiler, TMP_REG1, -local_size));
454 FAIL_IF(push_inst(compiler, SAVE | D(SLJIT_SP) | S1(SLJIT_SP) | S2(TMP_REG1), UNMOVABLE_INS));
596 arg2 = TMP_REG1;
617 arg2 = TMP_REG1;
653 /* arg1 goes to TMP_REG1 or src reg
656 result goes to TMP_REG2, so put result can use TMP_REG1 and TMP_REG3. */
677 else if ((dst & SLJIT_MEM) && !getput_arg_fast(compiler, flags | ARG_TEST, TMP_REG1, dst, dstw))
706 FAIL_IF(load_immediate(compiler, TMP_REG1, src1w));
707 src1_r = TMP_REG1;
[all...] |
| sljitNativeARM_32.c | 41 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2)
490 inst[1] = BLX | RM(TMP_REG1);
985 SLJIT_ASSERT(src1 == TMP_REG1); \
1001 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & ARGS_SWAPPED));
1013 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & ARGS_SWAPPED));
1033 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & ARGS_SWAPPED));
1091 FAIL_IF(push_inst(compiler, SMULL | (reg_map[TMP_REG1] << 16) | (reg_map[dst] << 12) | (reg_map[src2] << 8) | reg_map[src1]));
1093 /* cmp TMP_REG1, dst asr #31. */
1094 return push_inst(compiler, EMIT_DATA_PROCESS_INS(CMP_DP, SET_FLAGS, SLJIT_UNUSED, TMP_REG1, RM(dst) | 0xfc0));
1407 /* src1 is reg or TMP_REG1
[all...] |
| sljitNativePPC_64.c | 135 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \
136 src1 = TMP_REG1; \
146 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \
147 src1 = TMP_REG1; \
156 SLJIT_ASSERT(src1 == TMP_REG1);
163 SLJIT_ASSERT(src1 == TMP_REG1);
176 SLJIT_ASSERT(src1 == TMP_REG1);
191 SLJIT_ASSERT(src1 == TMP_REG1);
203 SLJIT_ASSERT(src1 == TMP_REG1);
208 SLJIT_ASSERT(src1 == TMP_REG1);
[all...] |
| sljitNativeX86_32.c | 113 PUSH_REG(reg_map[TMP_REG1]);
117 *inst++ = MOD_REG | (reg_map[TMP_REG1] << 3) | 0x4 /* esp */;
145 *inst++ = MOD_DISP8 | (reg_map[SLJIT_S0] << 3) | reg_map[TMP_REG1];
150 *inst++ = MOD_DISP8 | (reg_map[SLJIT_S1] << 3) | reg_map[TMP_REG1];
155 *inst++ = MOD_DISP8 | (reg_map[SLJIT_S2] << 3) | reg_map[TMP_REG1];
194 EMIT_MOV(compiler, TMP_REG1, 0, SLJIT_SP, 0);
203 TMP_REG1, 0, TMP_REG1, 0, SLJIT_IMM, sizeof(sljit_sw)));
215 return emit_mov(compiler, SLJIT_MEM1(SLJIT_SP), compiler->local_size, TMP_REG1, 0);
310 POP_REG(reg_map[TMP_REG1]);
[all...] |
| sljitNativePPC_common.c | 96 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2)
975 tmp_r = ((inp_flags & LOAD_DATA) && ((inp_flags) & MEM_MASK) <= GPR_REG) ? reg : TMP_REG1;
978 tmp_r = TMP_REG1;
1139 /* arg1 goes to TMP_REG1 or src reg
1142 result goes to TMP_REG2, so put result can use TMP_REG1 and TMP_REG3. */
1184 FAIL_IF(load_immediate(compiler, TMP_REG1, src1w));
1185 src1_r = TMP_REG1;
1187 else if (getput_arg_fast(compiler, input_flags | LOAD_DATA, TMP_REG1, src1, src1w)) {
1189 src1_r = TMP_REG1;
1217 FAIL_IF(getput_arg(compiler, input_flags | LOAD_DATA, TMP_REG1, src1, src1w, dst, dstw))
[all...] |
| sljitNativePPC_32.c | 54 SLJIT_ASSERT(src1 == TMP_REG1);
61 SLJIT_ASSERT(src1 == TMP_REG1);
76 SLJIT_ASSERT(src1 == TMP_REG1);
88 SLJIT_ASSERT(src1 == TMP_REG1);
92 SLJIT_ASSERT(src1 == TMP_REG1);
96 SLJIT_ASSERT(src1 == TMP_REG1);
|
| sljitNativeTILEGX_64.c | 48 #define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2)
1363 SLJIT_ASSERT(!(flags & LOAD_DATA) && reg_map[TMP_REG1] != reg_ar);
1594 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
1601 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
1616 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
1631 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
1645 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
1654 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
1963 /* arg1 goes to TMP_REG1 or src reg.
1966 result goes to TMP_REG2, so put result can use TMP_REG1 and TMP_REG3. *
[all...] |
| sljitNativeX86_64.c | 596 dst = TMP_REG1;
632 FAIL_IF(emit_load_imm64(compiler, TMP_REG1, srcw));
633 src = TMP_REG1;
716 dst_r = FAST_IS_REG(dst) ? dst : TMP_REG1;
|
