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    Searched refs:TReg (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
EarlyIfConversion.cpp 114 unsigned TReg, FReg;
115 // Latencies from Cond+Branch, TReg, and FReg to DstReg.
119 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {}
517 PI.TReg = PI.PHI->getOperand(i).getReg();
521 assert(Register::isVirtualRegister(PI.TReg) && "Bad PHI");
526 PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles,
562 const TargetInstrInfo *TII, Register TReg,
564 if (TReg == FReg)
567 if (!TReg.isVirtual() || !FReg.isVirtual())
570 const MachineInstr *TDef = MRI.getUniqueVRegDef(TReg);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelLowering.cpp 2342 // lds %TReg, 0(%Tmp1, %BReg)
2343 // bcfla %TReg
2345 Register TReg = MRI.createVirtualRegister(RC);
2351 BuildMI(DispContBB, DL, TII->get(VE::LDrri), TReg)
2356 .addReg(TReg, getKillRegState(true))
2366 // adds.l %TReg, %BReg2, %OReg
2367 // bcfla %TReg
2371 Register TReg = MRI.createVirtualRegister(RC);
2384 BuildMI(DispContBB, DL, TII->get(VE::ADDSLrr), TReg)
2388 .addReg(TReg, getKillRegState(true)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMAsmPrinter.cpp 1380 Register TReg = MI->getOperand(0).getReg();
1383 if (TIP.first == TReg) {
1391 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZInstrInfo.cpp 589 Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
591 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
593 TrueReg = TReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 4862 unsigned TReg = Inst.getOperand(2).getReg();
4876 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4882 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
4907 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4909 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
4987 unsigned TReg = Inst.getOperand(2).getReg();
5001 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
5007 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
5032 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
5034 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 4734 SDValue TReg = getI8Imm(TIndex, dl);
4743 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, TReg, Chain };
4746 SDValue Ops[] = { TReg, Base, Scale, Index, Disp, Segment, Chain };
X86ISelLowering.cpp     [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 3094 const Register TReg = I.getOperand(2).getReg();
3106 if (!emitSelect(I.getOperand(0).getReg(), TReg, FReg, AArch64CC::NE, MIB))

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