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    Searched refs:TargetRegisterClass (Results 1 - 25 of 341) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86RegisterInfo.h 60 const TargetRegisterClass *
61 getMatchingSuperRegClass(const TargetRegisterClass *A,
62 const TargetRegisterClass *B,
65 const TargetRegisterClass *
66 getSubClassWithSubReg(const TargetRegisterClass *RC,
69 const TargetRegisterClass *
70 getLargestLegalSuperClass(const TargetRegisterClass *RC,
73 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
75 const TargetRegisterClass *SrcRC,
78 /// getPointerRegClass - Returns a TargetRegisterClass used for pointe
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRRegisterInfo.h 35 const TargetRegisterClass *
36 getLargestLegalSuperClass(const TargetRegisterClass *RC,
46 const TargetRegisterClass *
55 const TargetRegisterClass *SrcRC,
57 const TargetRegisterClass *DstRC,
59 const TargetRegisterClass *NewRC,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.h 108 const TargetRegisterClass *getPointerRegClass(
141 const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) const;
144 const TargetRegisterClass *getAGPRClassForBitWidth(unsigned BitWidth) const;
147 static const TargetRegisterClass *getSGPRClassForBitWidth(unsigned BitWidth);
151 const TargetRegisterClass *getPhysRegClass(MCRegister Reg) const;
154 bool isSGPRClass(const TargetRegisterClass *RC) const {
166 bool isAGPRClass(const TargetRegisterClass *RC) const {
171 bool hasVGPRs(const TargetRegisterClass *RC) const;
174 bool hasAGPRs(const TargetRegisterClass *RC) const;
177 bool hasVectorRegisters(const TargetRegisterClass *RC) const
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonRegisterInfo.h 59 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
61 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
69 unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
73 const TargetRegisterClass *RC) const;
77 const TargetRegisterClass *
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
RegisterClassInfo.h 73 void compute(const TargetRegisterClass *RC) const;
76 const RCInfo &get(const TargetRegisterClass *RC) const {
92 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
99 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
109 bool isProperSubClass(const TargetRegisterClass *RC) const {
125 uint8_t getMinCost(const TargetRegisterClass *RC) const {
133 unsigned getLastCostChange(const TargetRegisterClass *RC) const {
TargetRegisterInfo.h 46 class TargetRegisterClass {
50 using sc_iterator = const TargetRegisterClass* const *;
117 /// Return true if the specified TargetRegisterClass
118 /// is a proper sub-class of this TargetRegisterClass.
119 bool hasSubClass(const TargetRegisterClass *RC) const {
124 bool hasSubClassEq(const TargetRegisterClass *RC) const {
129 /// Return true if the specified TargetRegisterClass is a
130 /// proper super-class of this TargetRegisterClass.
131 bool hasSuperClass(const TargetRegisterClass *RC) const {
136 bool hasSuperClassEq(const TargetRegisterClass *RC) const
    [all...]
LiveStacks.h 28 class TargetRegisterClass;
43 std::map<int, const TargetRegisterClass *> S2RCMap;
62 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
80 const TargetRegisterClass *getIntervalRegClass(int Slot) const {
82 std::map<int, const TargetRegisterClass *>::const_iterator I =
MachineSSAUpdater.h 26 class TargetRegisterClass;
44 const TargetRegisterClass *VRC;
65 void Initialize(const TargetRegisterClass *RC);
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kRegisterInfo.h 60 const TargetRegisterClass *
69 const TargetRegisterClass *RC) const;
74 const TargetRegisterClass *getMaximalPhysRegClass(unsigned reg, MVT VT) const;
77 int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const;
104 const TargetRegisterClass *intRegClass(unsigned Size) const;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegisterCoalescer.h 22 class TargetRegisterClass;
57 const TargetRegisterClass *NewRC = nullptr;
109 const TargetRegisterClass *getNewRC() const { return NewRC; }
TargetRegisterInfo.cpp 193 const TargetRegisterClass *
194 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
200 const TargetRegisterClass *SubRC = getRegClass(It.getID());
210 const TargetRegisterClass *
217 const TargetRegisterClass* BestRC = nullptr;
218 for (const TargetRegisterClass* RC : regclasses()) {
228 const TargetRegisterClass *
235 const TargetRegisterClass *BestRC = nullptr;
236 for (const TargetRegisterClass *RC : regclasses()) {
248 const TargetRegisterClass *RC, BitVector &R)
    [all...]
CriticalAntiDepBreaker.h 33 class TargetRegisterClass;
53 std::vector<const TargetRegisterClass *> Classes;
106 const TargetRegisterClass *RC,
LiveStacks.cpp 57 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
69 const TargetRegisterClass *OldRC = S2RCMap[Slot];
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
Mips16RegisterInfo.h 33 const TargetRegisterClass *RC,
36 const TargetRegisterClass *intRegClass(unsigned Size) const override;
MipsRegisterInfo.h 25 class TargetRegisterClass;
47 const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
50 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
73 virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
MipsSERegisterInfo.h 29 const TargetRegisterClass *intRegClass(unsigned Size) const override;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMRegisterBankInfo.h 35 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
Thumb1InstrInfo.h 46 const TargetRegisterClass *RC,
52 const TargetRegisterClass *RC,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64RegisterInfo.h 23 class TargetRegisterClass;
64 const TargetRegisterClass *
65 getSubClassWithSubReg(const TargetRegisterClass *RC,
97 const TargetRegisterClass *
100 const TargetRegisterClass *
101 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
126 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
133 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
134 unsigned SubReg, const TargetRegisterClass *DstRC,
135 unsigned DstSubReg, const TargetRegisterClass *NewRC
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.h 124 const TargetRegisterClass *
133 const TargetRegisterClass *
134 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
158 const TargetRegisterClass *SrcRC,
160 const TargetRegisterClass *DstRC,
162 const TargetRegisterClass *NewRC,
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
RegisterBank.h 22 class TargetRegisterClass;
71 bool covers(const TargetRegisterClass &RC) const;
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXRegisterInfo.h 59 std::string getNVPTXRegClassName(const TargetRegisterClass *RC);
60 std::string getNVPTXRegClassStr(const TargetRegisterClass *RC);
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRegisterInfo.h 25 class TargetRegisterClass;
44 const TargetRegisterClass *
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
RegisterBank.cpp 35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
61 bool RegisterBank::covers(const TargetRegisterClass &RC) const {
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430RegisterInfo.h 31 const TargetRegisterClass*

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