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    Searched refs:TempReg (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsFastISel.cpp 395 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
396 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
426 unsigned TempReg = createResultReg(RC);
427 emitInst(Mips::ADDiu, TempReg)
430 DestReg = TempReg;
652 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
653 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
654 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
658 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
659 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFrameLowering.cpp 654 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
689 &MBB, false, twoUniqueScratchRegsRequired(&MBB), &ScratchReg, &TempReg);
693 SingleScratchReg = ScratchReg == TempReg;
796 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFOCRF8), TempReg);
800 BuildMI(MBB, MBBI, dl, MoveFromCondRegInst, TempReg);
811 .addReg(TempReg, getKillRegState(true))
873 .addReg(TempReg, getKillRegState(true))
906 .addDef(TempReg) // TempReg stores the old sp.
913 .addReg(TempReg)
    [all...]
PPCISelDAGToDAG.cpp 451 Register TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
454 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
PPCISelLowering.cpp 11728 Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
11729 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg)
11733 .addReg(TempReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUTargetMachine.cpp 1264 Register TempReg;
1265 if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1269 RegVal = TempReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMExpandPseudoInsts.cpp 1588 Register TempReg = MI.getOperand(1).getReg();
1652 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg)
1661 .addReg(TempReg, RegState::Kill)
1716 Register TempReg = MI.getOperand(1).getReg();
1774 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg);
1781 .addReg(TempReg, RegState::Kill)
ARMFastISel.cpp 2965 Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
2968 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg)
2981 .addReg(TempReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/
RISCVAsmParser.cpp 2476 unsigned TempReg = Inst.getOperand(1).getReg();
2477 if (DestReg == TempReg) {
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
GlobalISelEmitter.cpp 3590 unsigned TempReg);
4578 // Assign the result to TempReg.

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