HomeSort by: relevance | last modified time | path
    Searched refs:TheDef (Results 1 - 25 of 39) sorted by relevancy

1 2

  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
SubtargetFeatureInfo.h 25 Record *TheDef;
30 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
34 return "Feature_" + TheDef->getName().str();
40 return "Feature_" + TheDef->getName().str() + "Bit";
44 return TheDef->getValueAsBit("RecomputePerFunction");
X86EVEX2VEXTablesEmitter.cpp 69 OS << " { X86::" << Pair.first->TheDef->getName()
70 << ", X86::" << Pair.second->TheDef->getName() << " },\n";
111 Record *RecE = EVEXInst->TheDef;
112 Record *RecV = VEXInst->TheDef;
193 Inst->TheDef->getValueAsListOfDefs("Predicates");
210 if (!Inst->TheDef->isSubClassOf("X86Inst"))
215 if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncVEX") {
216 uint64_t Opcode = getValueFromBitsInit(Inst->TheDef->
221 else if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncEVEX" &&
222 !Inst->TheDef->getValueAsBit("hasEVEX_K") &
    [all...]
AsmWriterInst.cpp 94 CGI.TheDef->getLoc(),
96 CGI.TheDef->getName() + "'!");
134 CGI.TheDef->getLoc(),
136 CGI.TheDef->getName() + "'");
143 CGI.TheDef->getLoc(),
145 CGI.TheDef->getName() + "'");
153 PrintFatalError(CGI.TheDef->getLoc(),
155 CGI.TheDef->getName() + "'");
160 CGI.TheDef->getLoc(),
162 CGI.TheDef->getName() + "'")
    [all...]
SubtargetFeatureInfo.cpp 20 errs() << getEnumName() << " " << Index << "\n" << *TheDef;
101 StringRef CondStr = SFI.TheDef->getValueAsString("CondString");
122 const DagInit *D = SFI.TheDef->getValueAsDag("AssemblerCondDag");
125 PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!");
127 PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!");
139 PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!");
145 PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!");
RegisterBankEmitter.cpp 35 const Record &TheDef;
44 RegisterBank(const Record &TheDef)
45 : TheDef(TheDef), RCs(), RCWithLargestRegsSize(nullptr) {}
48 StringRef getName() const { return TheDef.getValueAsString("Name"); }
50 std::string getEnumeratorName() const { return (TheDef.getName() + "ID").str(); }
54 return (TheDef.getName() + "CoverageData").str();
58 StringRef getInstanceVarName() const { return TheDef.getName(); }
60 const Record &getDef() const { return TheDef; }
X86FoldTablesEmitter.cpp 82 return Inst->TheDef->getName().find(InstStr) != StringRef::npos;
88 return Inst->TheDef->getName().find(InstStr) != StringRef::npos;
114 OS << "{ X86::" << RegInst->TheDef->getName() << ",";
116 OS << "X86::" << MemInst->TheDef->getName() << ",";
132 bool LHSpseudo = RegInst->TheDef->getValueAsBit("isPseudo");
133 bool RHSpseudo = RHS.RegInst->TheDef->getValueAsBit("isPseudo");
137 return RegInst->TheDef->getName() < RHS.RegInst->TheDef->getName();
305 StringRef AltRegInstStr = I->TheDef->getValueAsString("FoldGenRegForm");
323 Record *MemRec = MemInst->TheDef;
    [all...]
CodeBeadsGen.cpp 62 Record *R = CGI->TheDef;
81 Record *R = CGI->TheDef;
GICombinerEmitter.cpp 142 const Record &TheDef;
193 : ID(ID), TheDef(R), MatchDag(Ctx) {}
201 StringRef getName() const { return TheDef.getName(); }
202 const Record &getDef() const { return TheDef; }
248 PrintError(TheDef.getLoc(), "One or more roots are unnecessary");
349 DagInit *Defs = TheDef.getValueAsDag("Defs");
351 if (Defs->getOperatorAsDef(TheDef.getLoc())->getName() != "defs") {
352 PrintError(TheDef.getLoc(), "Expected defs operator");
376 PrintError(TheDef.getLoc(),
379 PrintError(TheDef.getLoc()
    [all...]
InstrInfoEmitter.cpp 242 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
255 Inst->TheDef->getName().str());
464 if (!Inst->TheDef->getValueAsBit("UseLogicalOperandMappings"))
480 (Namespace + "::" + Inst->TheDef->getName()).str());
551 if (!Inst->TheDef->getValueAsBit("UseLogicalOperandMappings"))
573 (Namespace + "::" + Inst->TheDef->getName()).str());
731 Record *Inst = II->TheDef;
761 InstrNames.add(std::string(Inst->TheDef->getName()));
779 OS << InstrNames.get(std::string(Inst->TheDef->getName())) << "U, ";
938 << Inst.TheDef->getValueAsInt("Size") << ",\t
    [all...]
CodeGenSchedule.cpp 121 StringRef InstName = Inst->TheDef->getName();
124 Elts.insert(Inst->TheDef);
134 return LHS->TheDef->getName() < RHS;
137 return LHS < RHS->TheDef->getName() &&
138 !RHS->TheDef->getName().startswith(LHS);
149 StringRef InstName = Inst->TheDef->getName();
151 Elts.insert(Inst->TheDef);
597 Record *SchedDef = Inst->TheDef;
673 findRWs(CGRW.TheDef->getValueAsListOfDefs("Writes"), CGRW.Sequence,
724 RWVec, [Def](const CodeGenSchedRW &RW) { return RW.TheDef == Def; })
    [all...]
CodeGenInstruction.cpp 27 CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
161 PrintFatalError(TheDef->getLoc(), "'" + TheDef->getName() +
182 PrintFatalError(TheDef->getLoc(),
183 TheDef->getName() + ": Illegal operand name: '" + Op + "'");
193 PrintFatalError(TheDef->getLoc(),
194 TheDef->getName() +
205 PrintFatalError(TheDef->getLoc(),
206 TheDef->getName() +
218 PrintFatalError(TheDef->getLoc(), TheDef->getName()
    [all...]
AsmWriterEmitter.cpp 132 << FirstInst.CGI->TheDef->getName() << ":\n";
135 << AWI.CGI->TheDef->getName() << ":\n";
147 FirstInst.CGI->TheDef->getName().str(),
152 AWI.CGI->TheDef->getName().str(),
190 InstrsForCase[idx] += Inst.CGI->TheDef->getName();
194 InstrsForCase.push_back(std::string(Inst.CGI->TheDef->getName()));
424 << NumberedInstructions[i]->TheDef->getName() << "\n";
561 AsmName = std::string(Reg.TheDef->getValueAsString("AsmName"));
567 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
577 Reg.TheDef->getValueAsListOfStrings("AltNames")
    [all...]
RISCVCompressInstEmitter.cpp 264 PrintFatalError(Inst.TheDef->getLoc(),
265 "Input operands for Inst '" + Inst.TheDef->getName() +
269 PrintFatalError(Inst.TheDef->getLoc(),
270 "Inst '" + Inst.TheDef->getName() +
281 PrintFatalError(Inst.TheDef->getLoc(),
282 "Inst '" + Inst.TheDef->getName() +
569 return (LHS.Source.TheDef->getName() < RHS.Source.TheDef->getName());
571 return (LHS.Dest.TheDef->getName() < RHS.Dest.TheDef->getName())
    [all...]
WebAssemblyDisassemblerEmitter.cpp 33 auto &Def = *CGI.TheDef;
66 auto IsCanonicalExisting = CGIP.second->TheDef->getValue("IsCanonical")
AsmMatcherEmitter.cpp 499 /// TheDef - This is the definition of the instruction or InstAlias that this
501 Record *const TheDef;
543 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI),
548 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
551 TheDef->getValueAsBit("UseInstAsmMatchConverter")) {
559 TheDef(RHS.TheDef), DefRec(RHS.DefRec), ResOperands(RHS.ResOperands),
801 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n"
    [all...]
CodeGenInstruction.h 140 Record *TheDef; // The actual record containing this OperandList.
220 Record *TheDef; // The actual record defining this instruction.
331 Record *TheDef; // The actual record defining this InstAlias.
CodeEmitterGen.cpp 358 Record *R = CGI->TheDef;
404 Record *R = CGI->TheDef;
551 for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) {
554 FeatureBitsets.back().push_back(I->second.TheDef);
613 for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) {
616 o << '_' << I->second.TheDef->getName();
622 o << ", // " << Inst->TheDef->getName() << " = " << InstIdx << "\n";
CodeGenRegisters.cpp 54 : TheDef(R), EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) {
64 : TheDef(nullptr), Name(std::string(N)), Namespace(std::string(Nspace)),
77 if (!TheDef)
80 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
83 PrintFatalError(TheDef->getLoc(),
89 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
93 TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
96 PrintFatalError(TheDef->getLoc(),
157 : TheDef(R), EnumValue(Enum),
166 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices")
    [all...]
SubtargetEmitter.cpp 832 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
833 return SchedWrite.TheDef;
839 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
840 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
845 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
848 AliasDef = AliasRW.TheDef;
859 || SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
873 SchedWrite.TheDef->getName());
883 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance"))
884 return SchedRead.TheDef;
    [all...]
CodeGenSchedule.h 40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
41 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
49 Record *TheDef;
59 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
77 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
83 assert((!HasVariants || TheDef) && "Variant write needs record def");
88 return TheDef || !Sequence.empty();
InstrDocsEmitter.cpp 70 Record *Inst = II->TheDef;
208 II->TheDef->getValueAsListOfDefs("Predicates");
CodeGenIntrinsics.h 27 Record *TheDef; // The actual record defining this intrinsic.
CodeGenRegisters.h 64 Record *const TheDef;
152 Record *TheDef;
168 // Extract more information from TheDef. This is used to build an object
302 Record *TheDef;
348 Record *getDef() const { return TheDef; }
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/GlobalISel/
GIMatchDagPredicate.cpp 33 OS << "$mi.getOpcode() == " << Instr.TheDef->getName();
45 OS << Separator << Instr->TheDef->getName();
GIMatchDagInstr.cpp 19 OS << Annotation->TheDef->getName();

Completed in 39 milliseconds

1 2