| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| IntrinsicLowering.cpp | 65 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8),
67 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16");
75 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8),
82 Tmp2 = Builder.CreateAnd(Tmp2,
86 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2");
87 V = Builder.CreateOr(Tmp4, Tmp2, "bswap.i32");
104 Value* Tmp2 = Builder.CreateLShr(V,
130 Tmp2 = Builder.CreateAnd(Tmp2
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 364 SDValue Tmp2 = Val;
388 Ch, dl, Tmp2, StackPtr2,
1653 SDValue Tmp2 = SDValue(Node, 1);
1661 SDValue Size = Tmp2.getOperand(1);
1677 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1681 Results.push_back(Tmp2);
2670 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2921 if (TLI.expandUINT_TO_FP(Node, Tmp1, Tmp2, DAG)) {
2924 Results.push_back(Tmp2);
2930 if ((Tmp1 = ExpandLegalINT_TO_FP(Node, Tmp2))) {
[all...] |
| SelectionDAG.cpp | 2104 SDValue Tmp2 = Node->getOperand(1);
2108 Tmp2, MachinePointerInfo(V));
2127 getStore(VAListLoad.getValue(1), dl, Tmp1, Tmp2, MachinePointerInfo(V));
3680 unsigned Tmp, Tmp2;
3711 Tmp2 = ComputeNumSignBits(SrcOp, Depth + 1);
3718 Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1);
3720 Tmp = std::min(Tmp, Tmp2);
3747 Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedRHS, Depth + 1)
[all...] |
| TargetLowering.cpp | 6629 SDValue Tmp2, Tmp3;
6631 Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt);
6634 Tmp2 = DAG.getNode(ISD::FSHR, dl, VT, ShOpHi, ShOpLo, ShAmt);
6647 Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2);
6650 Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2);
7177 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
7187 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
7191 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
7193 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1)
[all...] |
| LegalizeFloatTypes.cpp | 1820 SDValue Tmp1, Tmp2, Tmp3, OutputChain;
1824 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo,
1826 OutputChain = Tmp2->getNumValues() > 1 ? Tmp2.getValue(1) : SDValue();
1827 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1832 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi,
1834 OutputChain = Tmp2->getNumValues() > 1 ? Tmp2.getValue(1) : SDValue();
1835 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| IntegerDivision.cpp | 122 // ; %tmp2 = xor i32 %tmp, %dividend
123 // ; %u_dvnd = sub nsw i32 %tmp2, %tmp
132 Value *Tmp2 = Builder.CreateXor(Tmp, Dividend);
133 Value *U_Dvnd = Builder.CreateSub(Tmp2, Tmp);
266 // ; %tmp2 = sub i32 31, %sr
267 // ; %q = shl i32 %dividend, %tmp2
272 Value *Tmp2 = Builder.CreateSub(MSB, SR);
273 Value *Q = Builder.CreateShl(Dividend, Tmp2);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 3733 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
3734 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
3736 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)};
3769 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
3770 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
3771 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm,
3802 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
3803 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
3804 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm,
4070 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 1809 Register Tmp2 = MRI.createVirtualRegister(RC);
1815 // and %Tmp2, %Tmp1, (32)0
1816 // lea.sl %Result, TargetBB@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
1821 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2)
1826 .addReg(Tmp2, getKillRegState(true))
1831 // and %Tmp2, %Tmp1, (32)0
1832 // lea.sl %Result, TargetBB@hi(%Tmp2)
1837 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2)
1841 .addReg(Tmp2, getKillRegState(true))
1873 Register Tmp2 = MRI.createVirtualRegister(RC)
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/ |
| ExprEngineC.cpp | 49 ExplodedNodeSet Tmp2;
74 evalStore(Tmp2, B, LHS, *it, state->BindExpr(B, LCtx, ExprVal),
80 StmtNodeBuilder Bldr(*it, Tmp2, *currBldrCtx);
188 evalStore(Tmp2, B, LHS, *I, state, location, LHSVal);
193 getCheckerManager().runCheckersForPostStmt(Dst, Tmp2, B, *this);
|
| CheckerManager.cpp | 125 ExplodedNodeSet Tmp1, Tmp2;
133 CurrSet = (PrevSet == &Tmp1) ? &Tmp2 : &Tmp1;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 1959 SmallVector<MachineOperand,1> Tmp2;
1967 Tmp2.clear();
1968 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp2, false);
1971 if (TB != Header && (Tmp2.empty() || FB != Header))
1980 bool LatchNotAnalyzed = TII->analyzeBranch(*Latch, TB, FB, Tmp2, false);
|
| HexagonSplitDouble.cpp | 691 auto *Tmp2 =
693 HighI->addMemOperand(MF, Tmp2);
934 // Tmp2 = or R1.hi, Tmp1
935 // HiR = or (Tmp2, asl(R2.hi, #s))
|
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| ValueTracking.cpp | 2880 unsigned Tmp, Tmp2;
2965 Tmp2 = ShAmt->getZExtValue();
2966 return Tmp - Tmp2;
2976 Tmp2 = ComputeNumSignBits(U->getOperand(1), Depth + 1, Q);
2977 FirstAnswer = std::min(Tmp, Tmp2);
2994 Tmp2 = ComputeNumSignBits(U->getOperand(2), Depth + 1, Q);
2995 return std::min(Tmp, Tmp2);
3021 Tmp2 = ComputeNumSignBits(U->getOperand(1), Depth + 1, Q);
3022 if (Tmp2 == 1) break;
3023 return std::min(Tmp, Tmp2) - 1
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 1985 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1986 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2045 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2046 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2398 SDValue Tmp2 = ST->getBasePtr();
2403 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8,
|
| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| CGExprComplex.cpp | 856 llvm::Value *Tmp2 = Builder.CreateMul(LHSi, RHSi); // b*d
857 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPULegalizerInfo.cpp | 1901 auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign);
1907 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2);
3139 auto Tmp2 = B.buildFMA(ResTy, NegY, Ret, X);
3141 B.buildFMA(Res, Tmp2, R, Ret);
|
| AMDGPUISelLowering.cpp | 2196 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2198 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2214 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2225 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
|
| SIISelLowering.cpp | 3273 SDValue Tmp2 = Op.getValue(1);
3283 SDValue Size = Tmp2.getOperand(1);
3307 Tmp2 = DAG.getCALLSEQ_END(
3311 return DAG.getMergeValues({Tmp1, Tmp2}, dl);
8296 SDValue Tmp2 = DAG.getNode(ISD::FMA, SL, VT, NegY, Ret, X);
8297 return DAG.getNode(ISD::FMA, SL, VT, Tmp2, R, Ret);
9876 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1));
9879 SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3);
|
| SIInstrInfo.cpp | 571 Register Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
572 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs)
574 Tmp = Tmp2;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 5780 // tmp2 = VSPLTIS[BHW] -16
5781 // VSUBU[BHW]M tmp1, tmp2
5785 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
5787 SDValue(Tmp2, 0)));
5794 // tmp2 = VSPLTIS[BHW] -16
5795 // VADDU[BHW]M tmp1, tmp2
5799 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
5801 SDValue(Tmp2, 0)));
|
| PPCISelLowering.cpp | 8736 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
8738 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
8765 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
8767 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
8793 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
8795 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
11250 // andc tmp2, tmpDest, mask
11252 // or tmp4, tmp3, tmp2
12262 // andc tmp2, tmpDest, mask
12263 // or tmp4, tmp2, newval
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 7429 Register Tmp2 = MRI.createVirtualRegister(RC);
7430 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
7432 .addReg(Tmp2).addImm(-1);
7712 Register Tmp2 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7715 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Tmp2)
7718 .addReg(Tmp2).addReg(Lo).addImm(SystemZ::subreg_l64);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 3963 SDValue Tmp2 = CurDAG->getTargetConstant(CC, dl, MVT::i32);
3964 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
|
| ARMISelLowering.cpp | 6034 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
6035 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
6074 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
6075 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
|
