| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64SpeculationHardening.cpp | 161 unsigned TmpReg) const;
307 unsigned TmpReg = RS.FindUnusedReg(&AArch64::GPR64commonRegClass);
309 << ((TmpReg == 0) ? "no register " : "register ");
310 if (TmpReg != 0) dbgs() << printReg(TmpReg, TRI) << " ";
312 if (TmpReg == 0)
315 ReturnInstructions.push_back({&MI, TmpReg});
317 CallInstructions.push_back({&MI, TmpReg});
384 unsigned TmpReg) const {
393 .addDef(TmpReg)
[all...] |
| AArch64FastISel.cpp | 413 unsigned TmpReg = createResultReg(RC);
414 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg)
420 .addReg(TmpReg, getKillRegState(true));
4078 Register TmpReg = MRI.createVirtualRegister(RC);
4080 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
4084 Op0 = TmpReg;
4194 Register TmpReg = MRI.createVirtualRegister(RC);
4196 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
4200 Op0 = TmpReg;
4299 Register TmpReg = MRI.createVirtualRegister(RC)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 2728 unsigned TmpReg = DstReg;
2736 TmpReg = ATReg;
2756 unsigned TmpReg = DstReg;
2758 TmpReg = getATReg(IDLoc);
2759 if (!TmpReg)
2763 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI);
2765 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI);
2778 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI);
2779 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 153 unsigned TmpReg = createResultReg(ToRC);
155 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
156 return TmpReg;
1021 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1022 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
1024 SrcReg = TmpReg;
1116 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1117 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
1120 SrcReg = TmpReg;
1443 unsigned TmpReg = createResultReg(RC)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRExpandPseudoInsts.cpp | 622 Register TmpReg = 0; // 0 for no temporary register
631 TmpReg = scavengeGPR8(MI);
633 Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
634 Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
642 if (TmpReg)
643 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
651 if (TmpReg) {
653 buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg);
733 Register TmpReg = 0; // 0 for no temporary register
747 TmpReg = scavengeGPR8(MI)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 287 Register TmpReg =
290 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
302 MIB.addReg(TmpReg, getKillRegState(true))
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
|
| ThumbRegisterInfo.cpp | 512 Register TmpReg = MI.getOperand(0).getReg();
516 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
519 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
523 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
528 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
|
| Thumb1FrameLowering.cpp | 585 unsigned &TmpReg) {
586 PopReg = TmpReg = 0;
592 TmpReg = 0;
597 TmpReg = Reg;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRCopies.cpp | 275 Register TmpReg = MRI.createVirtualRegister(NewSrcRC);
278 TmpReg)
288 .addReg(TmpReg, RegState::Kill);
289 TmpReg = TmpAReg;
292 MI.getOperand(I).setReg(TmpReg);
598 Register TmpReg
602 TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg)
604 MI.getOperand(1).setReg(TmpReg);
|
| SIRegisterInfo.cpp | 1133 Register TmpReg;
1208 if (!TmpReg) {
1211 TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
1212 RS->setRegUsed(TmpReg);
1216 TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64), TmpReg)
1222 SubReg = TmpReg;
1252 if (!IsStore && TmpReg != AMDGPU::NoRegister) {
1255 .addReg(TmpReg, RegState::Kill);
1678 Register TmpReg = RS->scavengeRegister(RC, MI, 0, !UseSGPR);
1679 FIOp.setReg(TmpReg);
[all...] |
| SILowerI1Copies.cpp | 697 unsigned TmpReg = createLaneMaskReg(*MF);
698 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg)
701 MI.getOperand(1).setReg(TmpReg);
702 SrcReg = TmpReg;
|
| SIWholeQuadMode.cpp | 914 Register TmpReg;
941 TmpReg = MRI->createVirtualRegister(TRI->getBoolRC());
943 BuildMI(MBB, MI, DL, TII->get(XorOpc), TmpReg).add(Op).addReg(Exec);
946 .addReg(TmpReg);
1007 if (TmpReg)
1008 LIS->createAndComputeVirtRegInterval(TmpReg);
|
| AMDGPUInstructionSelector.cpp | 1646 Register TmpReg = MRI->createVirtualRegister(
1650 MIB.addDef(TmpReg);
1653 .addReg(TmpReg, RegState::Kill, SubReg);
2381 Register TmpReg = MRI->createVirtualRegister(
2401 auto MIB = BuildMI(*BB, &MI, DL, TII.get(Opcode), TmpReg)
2418 .addReg(TmpReg, RegState::Kill, SubReg);
2905 Register TmpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
2906 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::S_LSHR_B32), TmpReg)
2910 .addReg(TmpReg)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86SpeculativeLoadHardening.cpp | 1535 Register TmpReg = MRI->createVirtualRegister(PS->RC);
1539 auto ShiftI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHL64ri), TmpReg)
1546 .addReg(TmpReg, RegState::Kill);
1556 Register TmpReg = MRI->createVirtualRegister(PS->RC);
1561 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), TmpReg)
1565 .addReg(TmpReg, RegState::Kill)
1663 Register TmpReg = MRI->createVirtualRegister(OpRC);
1698 TII->get(Is128Bit ? X86::VPORrr : X86::VPORYrr), TmpReg)
1729 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOp), TmpReg)
1742 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), TmpReg)
[all...] |
| X86CmovConversion.cpp | 758 Register TmpReg = MRI->createVirtualRegister(RC);
761 bool Unfolded = TII->unfoldMemoryOperand(*MBB->getParent(), MI, TmpReg,
803 FalseBBRegRewriteTable[NewCMOV->getOperand(0).getReg()] = TmpReg;
|
| X86FlagsCopyLowering.cpp | 834 Register TmpReg = MRI->createVirtualRegister(PromoteRC);
837 .addDef(TmpReg, RegState::Dead)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFMISimplifyPatchable.cpp | 179 Register TmpReg = I->getParent()->getOperand(0).getReg();
180 processDstReg(MRI, TmpReg, DstReg, GVal, false, IsAma);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| LegalizationArtifactCombiner.h | 1014 Register TmpReg;
1015 while (mi_match(Reg, MRI, m_Copy(m_Reg(TmpReg)))) {
1016 if (MRI.getType(TmpReg).isValid())
1017 Reg = TmpReg;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsTargetStreamer.cpp | 333 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
336 /// and pass the appropriate register in TmpReg.
339 unsigned TmpReg, SMLoc IDLoc,
361 // Generate the base address in TmpReg.
362 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
364 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
366 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 763 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
772 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
777 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
778 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
|
| MipsTargetStreamer.h | 163 int64_t Offset, unsigned TmpReg, SMLoc IDLoc,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEInstrInfo.cpp | 376 Register TmpReg = VE::SX16;
377 Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32);
378 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg)
386 MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/ |
| RISCVAsmParser.cpp | 105 void emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg,
2231 void RISCVAsmParser::emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg,
2237 // TmpLabel: AUIPC TmpReg, VKHi(symbol)
2238 // OP DestReg, TmpReg, %pcrel_lo(TmpLabel)
2246 Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi));
2254 .addOperand(TmpReg)
2339 MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx);
2341 emitAuipcInstPair(DestReg, TmpReg, Symbol, RISCVMCExpr::VK_RISCV_PCREL_HI,
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TwoAddressInstructionPass.cpp | 226 Register TmpReg = FromReg;
228 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI);
232 TmpReg = Def->getOperand(1).getReg();
234 if (TmpReg == ToReg)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 426 unsigned BaseReg, IndexReg, TmpReg, Scale;
451 TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0),
656 BaseReg = TmpReg;
662 IndexReg = TmpReg;
717 BaseReg = TmpReg;
723 IndexReg = TmpReg;
774 TmpReg = Reg;
868 IndexReg = TmpReg;
965 BaseReg = TmpReg;
968 IndexReg = TmpReg;
[all...] |
