HomeSort by: relevance | last modified time | path
    Searched refs:TrueReg (Results 1 - 16 of 16) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZInstrInfo.h 243 ArrayRef<MachineOperand> Cond, Register TrueReg,
SystemZInstrInfo.cpp 535 Register DstReg, Register TrueReg,
548 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
571 Register TrueReg,
591 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
593 TrueReg = TReg;
605 .addReg(FalseReg).addReg(TrueReg)
SystemZISelLowering.cpp 7132 Register TrueReg = MI->getOperand(1).getReg();
7139 std::swap(TrueReg, FalseReg);
7141 if (RegRewriteTable.find(TrueReg) != RegRewriteTable.end())
7142 TrueReg = RegRewriteTable[TrueReg].first;
7149 .addReg(TrueReg).addMBB(TrueMBB)
7153 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg);
7238 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCMIPeephole.cpp 624 unsigned TrueReg =
626 if (!Register::isVirtualRegister(TrueReg))
628 MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
687 unsigned TrueReg =
689 if (!Register::isVirtualRegister(TrueReg))
691 MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
PPCInstrInfo.cpp 1533 Register DstReg, Register TrueReg,
1547 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1572 ArrayRef<MachineOperand> Cond, Register TrueReg,
1580 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1581 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
1632 Register FirstReg = SwapOps ? FalseReg : TrueReg,
1633 SecondReg = SwapOps ? TrueReg : FalseReg;
3108 unsigned TrueReg, unsigned FalseReg,
3115 return Imm1 < Imm2 ? TrueReg : FalseReg;
3117 return Imm1 > Imm2 ? TrueReg : FalseReg
    [all...]
PPCInstrInfo.h 428 ArrayRef<MachineOperand> Cond, Register TrueReg,
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 787 auto TrueReg = MIB.getReg(2);
789 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
794 .addUse(TrueReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.h 304 Register TrueReg, Register FalseReg, int &CondCycles,
310 Register TrueReg, Register FalseReg) const override;
315 Register TrueReg, Register FalseReg) const;
SIInstrInfo.cpp 1048 Register TrueReg,
1064 .addReg(TrueReg)
1079 .addReg(TrueReg)
1093 .addReg(TrueReg)
1107 .addReg(TrueReg)
1119 .addReg(TrueReg)
1139 .addReg(TrueReg)
1157 .addReg(TrueReg)
2494 Register DstReg, Register TrueReg,
2501 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64InstrInfo.h 218 ArrayRef<MachineOperand> Cond, Register TrueReg,
AArch64InstrInfo.cpp 613 Register DstReg, Register TrueReg,
620 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
640 if (canFoldIntoCSel(MRI, TrueReg))
664 Register TrueReg, Register FalseReg) const {
767 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg);
772 TrueReg = FalseReg;
786 MRI.constrainRegClass(TrueReg, RC);
791 .addReg(TrueReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyFastISel.cpp 916 unsigned TrueReg = getRegForValue(Select->getTrueValue());
917 if (TrueReg == 0)
925 std::swap(TrueReg, FalseReg);
963 .addReg(TrueReg)
WebAssemblyISelLowering.cpp 409 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg;
415 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
449 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute);
453 .addReg(TrueReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrInfo.h 351 ArrayRef<MachineOperand> Cond, Register TrueReg,
X86InstrInfo.cpp 3308 Register DstReg, Register TrueReg,
3323 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3346 ArrayRef<MachineOperand> Cond, Register TrueReg,
3356 .addReg(TrueReg)
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetInstrInfo.h 844 /// instruction that chooses between TrueReg and FalseReg based on the
847 /// When successful, also return the latency in cycles from TrueReg,
856 /// @param TrueReg Virtual register to select when Cond is true.
859 /// @param TrueCycles Latency from TrueReg to select output.
863 Register TrueReg, Register FalseReg,
869 /// Insert a select instruction into MBB before I that will copy TrueReg to
882 /// @param TrueReg Virtual register to copy when Cond is true.
887 Register TrueReg, Register FalseReg) const {

Completed in 80 milliseconds