1 /* $NetBSD: meson_usbctrl.c,v 1.7 2025/10/25 06:57:10 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2021 Ryo Shimizu 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 17 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: meson_usbctrl.c,v 1.7 2025/10/25 06:57:10 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/types.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 37 #include <dev/fdt/fdtvar.h> 38 39 /* 40 * USB Glue registers: 0xffe09000 41 */ 42 43 /* usb2 phy ports control registers */ 44 #define MESONUSBCTRL_MAXPHYS 3 45 #define U2P_R0_REG(i) (0x20 * (i) + 0x00) 46 #define U2P_R0_DRV_VBUS __BIT(5) 47 #define U2P_R0_ID_PULLUP __BIT(4) 48 #define U2P_R0_POWER_ON_RESET __BIT(3) 49 #define U2P_R0_HAST_MODE __BIT(2) 50 #define U2P_R0_POWER_OK __BIT(1) 51 #define U2P_R0_HOST_DEVICE __BIT(0) 52 #define U2P_R1_REG(i) (0x20 * (i) + 0x04) 53 #define U2P_R1_VBUS_VALID __BIT(3) 54 #define U2P_R1_OTG_SESSION_VALID __BIT(2) 55 #define U2P_R1_ID_DIG __BIT(1) 56 #define U2P_R1_PHY_READY __BIT(0) 57 58 #define MESON_G12A_GLUE_OFFSET 0x80 59 60 /* glue registers */ 61 #define USB_R0_REG 0x00 62 #define USB_R0_U2D_ACT __BIT(31) 63 #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK __BITS(30,29) 64 #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK __BITS(28,19) 65 #define USB_R0_P30_LANE0_EXT_PCLK_REQ __BIT(18) 66 #define USB_R0_P30_LANE0_TX2RX_LOOPBACK __BIT(17) 67 #define USB_R1_REG 0x04 68 #define USB_R1_P30_PCS_TX_SWING_FULL_MASK __BITS(31,25) 69 #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK __BITS(24,19) 70 #define USB_R1_U3H_HOST_MSI_ENABLE __BIT(18) 71 #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT __BIT(17) 72 #define USB_R1_U3H_HOST_U3_PORT_DISABLE __BIT(16) 73 #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK __BITS(13,12) 74 #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK __BITS(9,7) 75 #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK __BITS(4,2) 76 #define USB_R1_U3H_PME_ENABLE __BIT(1) 77 #define USB_R1_U3H_BIGENDIAN_GS __BIT(0) 78 #define USB_R2_REG 0x08 79 #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK __BITS(31,26) 80 #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK __BITS(25,20) 81 #define USB_R3_REG 0x0c 82 #define USB_R3_P30_REF_SSP_EN __BIT(13) 83 #define USB_R3_P30_SSC_REF_CLK_SEL_MASK __BITS(12,4) 84 #define USB_R3_P30_SSC_RANGE_MASK __BITS(3,1) 85 #define USB_R3_P30_SSC_ENABLE __BIT(0) 86 #define USB_R4_REG 0x10 87 #define USB_R4_P21_ONLY __BIT(4) 88 #define USB_R4_MEM_PD_MASK __BITS(3,2) 89 #define USB_R4_P21_SLEEP_M0 __BIT(1) 90 #define USB_R4_P21_PORT_RESET_0 __BIT(0) 91 #define USB_R5_REG 0x14 92 #define USB_R5_ID_DIG_CNT_MASK __BITS(23,16) 93 #define USB_R5_ID_DIG_TH_MASK __BITS(15,8) 94 #define USB_R5_ID_DIG_IRQ __BIT(7) 95 #define USB_R5_ID_DIG_CURR __BIT(6) 96 #define USB_R5_ID_DIG_EN_1 __BIT(5) 97 #define USB_R5_ID_DIG_EN_0 __BIT(4) 98 #define USB_R5_ID_DIG_CFG_MASK __BITS(3,2) 99 #define USB_R5_ID_DIG_REG __BIT(1) 100 #define USB_R5_ID_DIG_SYNC __BIT(0) 101 102 #define USBCTRL_READ_REG(sc, reg) \ 103 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 104 #define USBCTRL_WRITE_REG(sc, reg, val) \ 105 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 106 107 #define USBCTRLGLUE_READ_REG(sc, reg) \ 108 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh + (sc)->sc_conf->glue_offset, (reg)) 109 #define USBCTRLGLUE_WRITE_REG(sc, reg, val) \ 110 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh + (sc)->sc_conf->glue_offset, (reg), (val)) 111 112 struct meson_usbctrl_config { 113 bus_addr_t glue_offset; 114 int num_phys; 115 }; 116 117 struct meson_usbctrl_config mesong12_conf = { 118 .glue_offset = MESON_G12A_GLUE_OFFSET, 119 .num_phys = 3, 120 }; 121 122 struct meson_usbctrl_config mesongxl_conf = { 123 .num_phys = 2 124 }; 125 126 127 static const struct device_compatible_entry compat_data[] = { 128 { .compat = "amlogic,meson-g12a-usb-ctrl", .data = &mesong12_conf }, 129 { .compat = "amlogic,meson-gxl-usb-ctrl", .data = &mesongxl_conf }, 130 131 DEVICE_COMPAT_EOL 132 }; 133 134 struct meson_usbctrl_softc { 135 device_t sc_dev; 136 bus_space_tag_t sc_bst; 137 bus_space_handle_t sc_bsh; 138 const struct meson_usbctrl_config *sc_conf; 139 struct fdtbus_regulator *sc_supply; 140 int sc_phandle; 141 u_int sc_nusb2phys; 142 u_int sc_nusb3phys; 143 }; 144 145 static void 146 meson_usbctrl_phy_count(struct meson_usbctrl_softc *sc) 147 { 148 149 for (size_t i = 0; i < sc->sc_conf->num_phys; i++) { 150 const char * phyname = fdtbus_get_string_index(sc->sc_phandle, 151 "phy-names", i); 152 if (strstr(phyname, "usb3") == NULL) 153 sc->sc_nusb2phys++; 154 else 155 sc->sc_nusb3phys++; 156 } 157 } 158 159 160 static void 161 meson_usbctrl_usb2_init(struct meson_usbctrl_softc *sc) 162 { 163 int i; 164 const char *p; 165 166 for (i = 0; i < sc->sc_conf->num_phys; i++) { 167 /* setup only for usb2 phys */ 168 p = fdtbus_get_string_index(sc->sc_phandle, "phy-names", i); 169 if (p == NULL || strstr(p, "usb2") == NULL) 170 continue; 171 172 USBCTRL_WRITE_REG(sc, U2P_R0_REG(i), 173 USBCTRL_READ_REG(sc, U2P_R0_REG(i)) | 174 U2P_R0_POWER_ON_RESET); 175 176 /* XXX: OTG not supported. always set HOST_DEVICE mode */ 177 USBCTRL_WRITE_REG(sc, U2P_R0_REG(i), 178 USBCTRL_READ_REG(sc, U2P_R0_REG(i)) | 179 U2P_R0_HOST_DEVICE); 180 181 USBCTRL_WRITE_REG(sc, U2P_R0_REG(i), 182 USBCTRL_READ_REG(sc, U2P_R0_REG(i)) & 183 ~U2P_R0_POWER_ON_RESET); 184 } 185 } 186 187 static void 188 meson_usbctrl_usb_glue_init(struct meson_usbctrl_softc *sc) 189 { 190 uint32_t val; 191 192 val = USBCTRLGLUE_READ_REG(sc, USB_R1_REG); 193 val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK; 194 val |= __SHIFTIN(0x20, USB_R1_U3H_FLADJ_30MHZ_REG_MASK); 195 USBCTRLGLUE_WRITE_REG(sc, USB_R1_REG, val); 196 197 val = USBCTRLGLUE_READ_REG(sc, USB_R5_REG); 198 val |= USB_R5_ID_DIG_EN_0; 199 USBCTRLGLUE_WRITE_REG(sc, USB_R5_REG, val); 200 201 val = USBCTRLGLUE_READ_REG(sc, USB_R5_REG); 202 val |= USB_R5_ID_DIG_EN_1; 203 USBCTRLGLUE_WRITE_REG(sc, USB_R5_REG, val); 204 205 val = USBCTRLGLUE_READ_REG(sc, USB_R5_REG); 206 val &= ~USB_R5_ID_DIG_TH_MASK; 207 val |= __SHIFTIN(0xff, USB_R5_ID_DIG_TH_MASK); 208 USBCTRLGLUE_WRITE_REG(sc, USB_R5_REG, val); 209 } 210 211 static void 212 meson_usbctrl_usb3_init(struct meson_usbctrl_softc *sc) 213 { 214 uint32_t val; 215 216 val = USBCTRLGLUE_READ_REG(sc, USB_R3_REG); 217 val &= ~USB_R3_P30_SSC_RANGE_MASK; 218 val &= ~USB_R3_P30_SSC_ENABLE; 219 val |= __SHIFTIN(2, USB_R3_P30_SSC_RANGE_MASK); 220 val |= USB_R3_P30_REF_SSP_EN; 221 USBCTRLGLUE_WRITE_REG(sc, USB_R3_REG, val); 222 223 delay(2); 224 225 val = USBCTRLGLUE_READ_REG(sc, USB_R2_REG); 226 val &= ~USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK; 227 val |= __SHIFTIN(0x15, USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK); 228 USBCTRLGLUE_WRITE_REG(sc, USB_R2_REG, val); 229 230 val = USBCTRLGLUE_READ_REG(sc, USB_R2_REG); 231 val &= ~USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK; 232 val |= __SHIFTIN(0x20, USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK); 233 USBCTRLGLUE_WRITE_REG(sc, USB_R2_REG, val); 234 235 delay(2); 236 237 val = USBCTRLGLUE_READ_REG(sc, USB_R1_REG); 238 val |= USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT; 239 USBCTRLGLUE_WRITE_REG(sc, USB_R1_REG, val); 240 241 val = USBCTRLGLUE_READ_REG(sc, USB_R1_REG); 242 val &= ~USB_R1_P30_PCS_TX_SWING_FULL_MASK; 243 val |= __SHIFTIN(127, USB_R1_P30_PCS_TX_SWING_FULL_MASK); 244 USBCTRLGLUE_WRITE_REG(sc, USB_R1_REG, val); 245 246 /* XXX: force HOST_DEVICE mode */ 247 val = USBCTRLGLUE_READ_REG(sc, USB_R0_REG); 248 val &= ~USB_R0_U2D_ACT; 249 USBCTRLGLUE_WRITE_REG(sc, USB_R0_REG, val); 250 251 val = USBCTRLGLUE_READ_REG(sc, USB_R4_REG); 252 val &= ~USB_R4_P21_SLEEP_M0; 253 USBCTRLGLUE_WRITE_REG(sc, USB_R4_REG, val); 254 } 255 256 static void 257 meson_usbctrl_enable_usb3_phys(struct meson_usbctrl_softc *sc) 258 { 259 struct fdtbus_phy *phy; 260 int i; 261 const char *phyname; 262 263 /* 264 * enable only for usb3 phys. 265 * node of "snps,dwc3" decl in "amlogic,meson-g12a-usb-ctrl" have 266 * no "phys" property, so enable the phy here. 267 */ 268 for (i = 0; i < sc->sc_conf->num_phys; i++) { 269 phyname = fdtbus_get_string_index(sc->sc_phandle, 270 "phy-names", i); 271 if (strstr(phyname, "usb3") == NULL) 272 continue; 273 274 phy = fdtbus_phy_get_index(sc->sc_phandle, i); 275 if (phy == NULL) 276 continue; 277 if (fdtbus_phy_enable(phy, true) != 0) 278 aprint_error_dev(sc->sc_dev, "couldn't enable phy %s\n", 279 phyname); 280 } 281 } 282 283 static int 284 meson_usbctrl_match(device_t parent, cfdata_t cf, void *aux) 285 { 286 struct fdt_attach_args * const faa = aux; 287 288 return of_compatible_match(faa->faa_phandle, compat_data); 289 } 290 291 static void 292 meson_usbctrl_attach(device_t parent, device_t self, void *aux) 293 { 294 struct meson_usbctrl_softc * const sc = device_private(self); 295 struct fdt_attach_args * const faa = aux; 296 bus_addr_t addr; 297 bus_size_t size; 298 int phandle, child; 299 300 sc->sc_dev = self; 301 sc->sc_bst = faa->faa_bst; 302 sc->sc_phandle = phandle = faa->faa_phandle; 303 sc->sc_conf = of_compatible_lookup(phandle, compat_data)->data; 304 305 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 306 aprint_error(": couldn't get registers\n"); 307 return; 308 } 309 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 310 aprint_error(": couldn't map registers\n"); 311 return; 312 } 313 314 aprint_naive("\n"); 315 aprint_normal(": USB Controllers\n"); 316 317 sc->sc_supply = fdtbus_regulator_acquire(phandle, "vbus-supply"); 318 if (sc->sc_supply != NULL) 319 fdtbus_regulator_enable(sc->sc_supply); /* USB HOST MODE */ 320 321 meson_usbctrl_phy_count(sc); 322 323 meson_usbctrl_usb2_init(sc); 324 meson_usbctrl_usb_glue_init(sc); 325 if (sc->sc_nusb3phys) { 326 meson_usbctrl_usb3_init(sc); 327 meson_usbctrl_enable_usb3_phys(sc); 328 } 329 330 for (child = OF_child(phandle); child; child = OF_peer(child)) { 331 fdt_add_child(parent, child, faa, 0); 332 } 333 } 334 335 CFATTACH_DECL_NEW(meson_usbctrl, sizeof(struct meson_usbctrl_softc), 336 meson_usbctrl_match, meson_usbctrl_attach, NULL, NULL); 337
Indexes created Sat Oct 25 16:10:12 GMT 2025