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Searched refs:U4_20 (Results 1 - 4 of 4) sorted by relevancy

/src/external/gpl3/binutils/dist/opcodes/
s390-opc.c	209 #define U4_20 (U4_16 + 1) /* 4 bit unsigned value starting at 20 / 211 #define U4_24 (U4_20 + 1) / 4 bit unsigned value starting at 24 / 366 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } / e.g. didbr / 367 #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } / e.g. qaxtr / 368 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } / e.g. adtra / 369 #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } / e.g. axtra / 370 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } / e.g. ipte / 371 #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } / e.g. lptea / 381 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } / e.g. fidtr / 382 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } / e.g. ldxtr * [all...]
/src/external/gpl3/binutils.old/dist/opcodes/
s390-opc.c	209 #define U4_20 (U4_16 + 1) /* 4 bit unsigned value starting at 20 / 211 #define U4_24 (U4_20 + 1) / 4 bit unsigned value starting at 24 / 366 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } / e.g. didbr / 367 #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } / e.g. qaxtr / 368 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } / e.g. adtra / 369 #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } / e.g. axtra / 370 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } / e.g. ipte / 371 #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } / e.g. lptea / 381 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } / e.g. fidtr / 382 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } / e.g. ldxtr * [all...]
/src/external/gpl3/gdb/dist/opcodes/
s390-opc.c	209 #define U4_20 (U4_16 + 1) /* 4 bit unsigned value starting at 20 / 211 #define U4_24 (U4_20 + 1) / 4 bit unsigned value starting at 24 / 366 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } / e.g. didbr / 367 #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } / e.g. qaxtr / 368 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } / e.g. adtra / 369 #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } / e.g. axtra / 370 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } / e.g. ipte / 371 #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } / e.g. lptea / 381 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } / e.g. fidtr / 382 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } / e.g. ldxtr * [all...]
/src/external/gpl3/gdb.old/dist/opcodes/
s390-opc.c	207 #define U4_20 (U4_16 + 1) /* 4 bit unsigned value starting at 20 / 209 #define U4_24 (U4_20 + 1) / 4 bit unsigned value starting at 24 / 376 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } / e.g. didbr / 377 #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } / e.g. qaxtr / 378 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } / e.g. adtra / 379 #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } / e.g. axtra / 380 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } / e.g. ipte / 381 #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } / e.g. lptea / 391 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } / e.g. fidtr / 392 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } / e.g. ldxtr * [all...]

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