| /src/external/gpl3/binutils/dist/opcodes/ |
| mips16-opc.c | 163 #define UBD INSN_UNCOND_BRANCH_DELAY
325 {"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
326 {"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
327 {"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
328 {"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
329 {"jal", "a", 0x18000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
330 {"jalx", "i", 0x1c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
331 {"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
332 {"jr", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
333 {"j", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 }
[all...] |
| micromips-opc.c | 208 #define UBD INSN_UNCOND_BRANCH_DELAY
322 {"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1, 0, 0 },
323 {"b", "p", 0x94000000, 0xffff0000, UBD, AL, I1, 0, 0 }, /* beq 0, 0 */
324 {"b", "p", 0x40400000, 0xffff0000, UBD, AL, I1, 0, 0 }, /* bgez 0 */
328 {"bal", "p", 0x40600000, 0xffff0000, WR_31|UBD, BD32|AL, I1, 0, 0 }, /* bgezal 0 */
329 {"bals", "p", 0x42600000, 0xffff0000, WR_31|UBD, BD16|AL, I1, 0, 0 }, /* bgezals 0 */
732 {"jr", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 },
733 {"jr", "s", 0x00000f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr */
734 {"jrs", "s", 0x00004f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs */
739 {"jr.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr.hb *
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| mips16-opc.c | 163 #define UBD INSN_UNCOND_BRANCH_DELAY
325 {"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
326 {"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
327 {"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
328 {"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
329 {"jal", "a", 0x18000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
330 {"jalx", "i", 0x1c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
331 {"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
332 {"jr", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
333 {"j", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 }
[all...] |
| micromips-opc.c | 208 #define UBD INSN_UNCOND_BRANCH_DELAY
322 {"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1, 0, 0 },
323 {"b", "p", 0x94000000, 0xffff0000, UBD, AL, I1, 0, 0 }, /* beq 0, 0 */
324 {"b", "p", 0x40400000, 0xffff0000, UBD, AL, I1, 0, 0 }, /* bgez 0 */
328 {"bal", "p", 0x40600000, 0xffff0000, WR_31|UBD, BD32|AL, I1, 0, 0 }, /* bgezal 0 */
329 {"bals", "p", 0x42600000, 0xffff0000, WR_31|UBD, BD16|AL, I1, 0, 0 }, /* bgezals 0 */
732 {"jr", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 },
733 {"jr", "s", 0x00000f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr */
734 {"jrs", "s", 0x00004f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs */
739 {"jr.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr.hb *
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| mips16-opc.c | 163 #define UBD INSN_UNCOND_BRANCH_DELAY
325 {"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
326 {"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
327 {"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
328 {"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
329 {"jal", "a", 0x18000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
330 {"jalx", "i", 0x1c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
331 {"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
332 {"jr", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
333 {"j", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 }
[all...] |
| micromips-opc.c | 208 #define UBD INSN_UNCOND_BRANCH_DELAY
322 {"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1, 0, 0 },
323 {"b", "p", 0x94000000, 0xffff0000, UBD, AL, I1, 0, 0 }, /* beq 0, 0 */
324 {"b", "p", 0x40400000, 0xffff0000, UBD, AL, I1, 0, 0 }, /* bgez 0 */
328 {"bal", "p", 0x40600000, 0xffff0000, WR_31|UBD, BD32|AL, I1, 0, 0 }, /* bgezal 0 */
329 {"bals", "p", 0x42600000, 0xffff0000, WR_31|UBD, BD16|AL, I1, 0, 0 }, /* bgezals 0 */
732 {"jr", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 },
733 {"jr", "s", 0x00000f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr */
734 {"jrs", "s", 0x00004f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs */
739 {"jr.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr.hb *
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| mips16-opc.c | 163 #define UBD INSN_UNCOND_BRANCH_DELAY
325 {"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
326 {"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
327 {"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
328 {"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
329 {"jal", "a", 0x18000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
330 {"jalx", "i", 0x1c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
331 {"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
332 {"jr", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
333 {"j", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 }
[all...] |
| micromips-opc.c | 200 #define UBD INSN_UNCOND_BRANCH_DELAY
311 {"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1, 0, 0 },
312 {"b", "p", 0x94000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 }, /* beq 0, 0 */
313 {"b", "p", 0x40400000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 }, /* bgez 0 */
317 {"bal", "p", 0x40600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD32, I1, 0, 0 }, /* bgezal 0 */
318 {"bals", "p", 0x42600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD16, I1, 0, 0 }, /* bgezals 0 */
706 {"jr", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 },
707 {"jr", "s", 0x00000f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr */
708 {"jrs", "s", 0x00004f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs */
713 {"jr.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr.hb *
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/LiveDebugValues/ |
| InstrRefBasedImpl.cpp | 1116 UseBeforeDef UBD = {ID, Var, Properties};
1117 UseBeforeDefs[ID.getInst()].push_back(UBD);
|
