| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 604 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
607 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
609 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
611 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
613 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
615 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
617 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
619 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
621 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
623 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }
[all...] |
| ARMISelLowering.cpp | 174 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
179 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
309 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
903 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
909 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
910 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1035 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
5697 case ISD::UINT_TO_FP:
5699 Opc = ISD::UINT_TO_FP;
9861 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 1532 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
1533 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
1637 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
1638 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
1639 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 },
1640 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 },
1641 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
1642 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
1643 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
1644 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }
[all...] |
| X86IntrinsicsInfo.h | 918 X86_INTRINSIC_DATA(avx512_uitofp_round, INTR_TYPE_1OP, ISD::UINT_TO_FP, X86ISD::UINT_TO_FP_RND),
|
| X86ISelLowering.cpp | 228 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
230 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
232 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
236 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
240 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
849 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
1032 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
1035 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
1038 // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
1041 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 665 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
666 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
667 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
673 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
674 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
675 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
680 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
681 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
686 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 },
687 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }
[all...] |
| AArch64ISelLowering.cpp | 461 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
462 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
463 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
882 setTargetDAGCombine(ISD::UINT_TO_FP);
986 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
993 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i8, MVT::v4i32);
996 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i8, MVT::v8i32);
997 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v16i8, MVT::v16i32);
1002 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
1004 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 730 UINT_TO_FP,
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 476 case ISD::UINT_TO_FP:
576 case ISD::UINT_TO_FP:
648 unsigned Opc = (Node->getOpcode() == ISD::UINT_TO_FP ||
763 case ISD::UINT_TO_FP:
1269 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
|
| SelectionDAGDumper.cpp | 348 case ISD::UINT_TO_FP: return "uint_to_fp";
|
| LegalizeDAG.cpp | 1002 case ISD::UINT_TO_FP:
2510 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2519 unsigned UIntOp = IsStrict ? ISD::STRICT_UINT_TO_FP : ISD::UINT_TO_FP;
2540 // If the target supports UINT_TO_FP of this type, use it.
2919 case ISD::UINT_TO_FP:
4165 case ISD::UINT_TO_FP: {
4375 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4450 case ISD::UINT_TO_FP:
|
| LegalizeFloatTypes.cpp | 134 case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break;
1245 case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break;
1711 llvm_unreachable("Unsupported UINT_TO_FP!");
2269 case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break;
2632 case ISD::UINT_TO_FP: R = SoftPromoteHalfRes_XINT_TO_FP(N); break;
|
| LegalizeVectorTypes.cpp | 105 case ISD::UINT_TO_FP:
613 case ISD::UINT_TO_FP:
998 case ISD::UINT_TO_FP:
2184 case ISD::UINT_TO_FP:
3096 case ISD::UINT_TO_FP:
4556 case ISD::UINT_TO_FP:
|
| DAGCombiner.cpp | 1692 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
14420 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT &&
14444 // but UINT_TO_FP is legal on this target, try to convert.
14446 hasOperation(ISD::UINT_TO_FP, OpVT)) {
14447 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
14449 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
14488 // fold (uint_to_fp c1) -> c1fp
14493 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
14495 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
14497 if (!hasOperation(ISD::UINT_TO_FP, OpVT) &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 398 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
435 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
1258 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
1679 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1814 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo);
1815 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi);
2496 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2499 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2521 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext);
|
| R600ISelLowering.cpp | 1759 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1762 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1763 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0),
|
| SIISelLowering.cpp | 552 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Custom);
557 setOperationAction(ISD::UINT_TO_FP, MVT::f16, Promote);
817 setTargetDAGCombine(ISD::UINT_TO_FP);
9359 case ISD::UINT_TO_FP:
9490 if (VT == MVT::f32 && (N0.getOpcode() == ISD::UINT_TO_FP ||
10890 case ISD::UINT_TO_FP:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 154 setTargetDAGCombine(ISD::UINT_TO_FP);
221 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT})
2135 if (N->getOpcode() == ISD::SINT_TO_FP || N->getOpcode() == ISD::UINT_TO_FP) {
2169 IntToFP.getOpcode() != ISD::UINT_TO_FP)
2246 case ISD::UINT_TO_FP:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 239 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
240 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
260 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
486 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
500 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
638 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
669 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
679 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
865 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1049 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1519 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1521 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
3032 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
3379 case ISD::UINT_TO_FP:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 206 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); // use i64
208 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
2486 case ISD::UINT_TO_FP:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 1770 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1771 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1772 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 268 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
269 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
413 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
414 setOperationAction(ISD::UINT_TO_FP, MVT::v2f64, Legal);
433 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
434 setOperationAction(ISD::UINT_TO_FP, MVT::v4f32, Legal);
651 setTargetDAGCombine(ISD::UINT_TO_FP);
6349 // v2f64 = uint_to_fp v2i16
6351 // v2f64 = uint_to_fp (v2i64 zero_extend v2i16)
6356 (Opcode == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 1785 case UIToFP: return ISD::UINT_TO_FP;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 359 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
1871 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
|
