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    Searched refs:UMULO (Results 1 - 20 of 20) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 312 UMULO,
SelectionDAGNodes.h 2748 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 98 for (auto OP : {ISD::SMULO, ISD::UMULO}) {
1325 case ISD::UMULO:
2105 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) {
2128 case ISD::UMULO:
2139 if (CondOpcode == ISD::UMULO)
2146 if (CondOpcode == ISD::UMULO)
2327 case ISD::UMULO:
2342 if (CondOpcode == ISD::UMULO)
2349 if (CondOpcode == ISD::UMULO)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 450 case ISD::UMULO:
842 case ISD::UMULO:
SelectionDAGDumper.cpp 306 case ISD::UMULO: return "umulo";
LegalizeIntegerTypes.cpp 157 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
1379 if (N->getOpcode() == ISD::UMULO) {
2177 case ISD::UMULO:
3420 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
3936 if (N->getOpcode() == ISD::UMULO) {
3964 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfWithO, LHSHigh, RHSLow);
3967 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfWithO, RHSHigh, LHSLow);
LegalizeVectorTypes.cpp 174 case ISD::UMULO:
1069 case ISD::UMULO:
3069 case ISD::UMULO:
SelectionDAG.cpp 3076 case ISD::UMULO:
3900 case ISD::UMULO:
9991 Opcode == ISD::UMULO || Opcode == ISD::SMULO) &&
LegalizeDAG.cpp 3466 case ISD::UMULO:
TargetLowering.cpp 8114 } else if (!Signed && isOperationLegalOrCustom(ISD::UMULO, VT)) {
8116 DAG.getNode(ISD::UMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
8385 // smulo(x, signed_min) is same as umulo(x, signed_min).
8511 "Unexpected result type for S/UMULO legalization");
SelectionDAGBuilder.cpp 6719 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
DAGCombiner.cpp 1641 case ISD::UMULO: return visitMULO(N);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCTargetTransformInfo.cpp 556 case Intrinsic::umul_with_overflow: Opcode = ISD::UMULO; break;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 2754 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto
2779 { ISD::UMULO, MVT::i32, 2 }, // mul + seto
2780 { ISD::UMULO, MVT::i16, 2 },
2781 { ISD::UMULO, MVT::i8, 2 },
2856 ISD = ISD::UMULO;
X86ISelLowering.cpp 946 setOperationAction(ISD::UMULO, MVT::v16i8, Custom);
1349 setOperationAction(ISD::UMULO, MVT::v32i8, Custom);
1648 setOperationAction(ISD::UMULO, MVT::v64i8, Custom);
1953 setOperationAction(ISD::UMULO, VT, Custom);
23560 case ISD::UMULO:
23820 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1683 setOperationAction(ISD::UMULO, MVT::i64, Custom);
2937 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2943 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
3063 case ISD::UMULO:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 779 setOperationAction(ISD::UMULO, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 557 setOperationAction(ISD::UMULO, MVT::i32, Custom);
558 setOperationAction(ISD::UMULO, MVT::i64, Custom);
2946 case ISD::UMULO: {
4507 case ISD::UMULO:
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 764 setOperationAction(ISD::UMULO, MVT::i64, Custom);
4553 case ISD::UMULO:
5143 // smulo(x, signed_min) is same as umulo(x, signed_min).
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 4717 case ISD::UMULO:
5445 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5496 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&

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