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    Searched refs:UNINDEXED (Results 1 - 17 of 17) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 1266 /// UNINDEXED "Normal" load / store. The effective address is already
1269 /// chain, an unindexed load produces one value (result of the
1270 /// load); an unindexed store does not produce a value.
1272 /// PRE_INC Similar to the unindexed mode where the effective address is
1290 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC };
SelectionDAGNodes.h 2233 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2239 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2242 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2334 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2340 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2343 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2665 /// Returns true if the specified node is a non-extending and unindexed load.
2669 Ld->getAddressingMode() == ISD::UNINDEXED;
2696 /// Returns true if the specified node is an unindexed load.
2699 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
    [all...]
BasicTTIImpl.h 179 return ISD::UNINDEXED;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLoweringHVX.cpp 1855 Thru.first, SingleTy, MOp0, ISD::UNINDEXED,
1859 Thru.second, SingleTy, MOp1, ISD::UNINDEXED,
1870 ISD::UNINDEXED, false, false);
1873 ISD::UNINDEXED, false, false);
1908 ISD::UNINDEXED, ISD::NON_EXTLOAD, false);
1944 MemOp, ISD::UNINDEXED, false, false);
HexagonISelDAGToDAG.cpp 451 if (AM != ISD::UNINDEXED) {
560 if (AM != ISD::UNINDEXED) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAG.cpp 7313 bool Indexed = AM != ISD::UNINDEXED;
7314 assert((Indexed || Offset.isUndef()) && "Unindexed load with an offset!");
7347 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
7354 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
7365 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, PtrInfo,
7373 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
7424 dl.getIROrder(), VTs, ISD::UNINDEXED, false, VT, MMO));
7432 ISD::UNINDEXED, false, VT, MMO);
7490 dl.getIROrder(), VTs, ISD::UNINDEXED, true, SVT, MMO));
7498 ISD::UNINDEXED, true, SVT, MMO)
    [all...]
LegalizeVectorTypes.cpp 359 ISD::UNINDEXED, N->getExtensionType(),
1708 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1715 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, MPI,
SelectionDAGBuilder.cpp 4333 ISD::UNINDEXED, false /* Truncating */, IsCompressing);
4511 ISD::UNINDEXED, ISD::NON_EXTLOAD, IsExpanding);
TargetLowering.cpp 7461 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
7613 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
DAGCombiner.cpp 7513 assert(L->getOffset().isUndef() && "Unindexed load must have undef offset");
15103 ISD::MemIndexedMode AM = ISD::UNINDEXED;
15397 ISD::MemIndexedMode AM = ISD::UNINDEXED;
15440 assert(AM != ISD::UNINDEXED);
15650 // Unindexed loads.
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 1577 if (AM == ISD::UNINDEXED)
1683 if (AM == ISD::UNINDEXED)
1742 if (AM == ISD::UNINDEXED)
1758 if (AM == ISD::UNINDEXED)
ARMISelLowering.cpp 9496 assert(LD->isUnindexed() && "Expected a unindexed load");
9529 assert(LD->isUnindexed() && "Loads should be unindexed at this point.");
9551 assert(ST->isUnindexed() && "Expected a unindexed store");
9585 assert(ST->isUnindexed() && "Stores should be unindexed at this point.");
15105 // transform is only legal for unindexed loads.
16241 DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 1547 ISD::UNINDEXED, Ext, VT, DL, Chain,
SIISelLowering.cpp 7979 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 778 LD->getAddressingMode() != ISD::UNINDEXED ||
X86ISelLowering.cpp     [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 14280 ISD::UNINDEXED, ISD::NON_EXTLOAD, false);
14363 ISD::UNINDEXED, false, false);

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