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Searched refs:UPLL_RESET_MASK (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv770.c	`90 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK \| UPLL_SLEEP_MASK)); 101 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 119 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);`
rv770d.h	`45 # define UPLL_RESET_MASK 0x00000001`
radeon_r600.c	`222 UPLL_RESET_MASK \| UPLL_SLEEP_MASK \| UPLL_CTLREQ_MASK)); 255 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 279 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);`
radeon_evergreen.c	`1231 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 1240 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 1265 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);`
radeon_si.c	`7045 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 7054 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 7079 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);`
sid.h	`130 # define UPLL_RESET_MASK 0x00000001`
evergreend.h	`351 # define UPLL_RESET_MASK 0x00000001`
r600d.h	`1559 # define UPLL_RESET_MASK 0x00000001`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h	`132 # define UPLL_RESET_MASK 0x00000001`

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