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  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
xlnx-zynqmp-clk.h 49 #define USB0 35
  /src/sys/arch/arm/marvell/
orionreg.h 183 #define ORION_USB0_BASE (ORION_UNITID2PHYS(USB0)) /* 0x50000 */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
sun8i-h2-plus-bananapi-m2-zero.dts 252 "VCC-IO-EN", "USB0-ID", "WL-PWR-EN",
gemini.dtsi 432 * This will claim pins for USB0 and USB1 at the same
435 * NOT using USB0 at 68000000 you wll have to add the
am335x-pepper.dts 557 &usb0 {
568 /* USB0 Over-Current (active low) */
imx6qdl-kontron-samx6i.dtsi 773 /* USB0 */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/
k3-j7200-common-proc-board.dts 297 idle-states = <1>; /* USB0 to SERDES lane 3 */
307 &usb0 {
k3-j721e-common-proc-board.dts 344 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
377 &usb0 {
k3-j7200-main.dtsi 45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
652 usb0: usb@6000000 { label in label:usbss0
k3-j721e-main.dtsi 66 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
1121 usb0: usb@6000000 { label in label:usbss0
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/xilinx/
zynqmp-zcu102-revA.dts 235 output-high; /* PCIE = 0, USB0 = 1 */
691 &usb0 {

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