| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 330 USUBSAT,
|
| TargetLowering.h | 2467 case ISD::USUBSAT:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 2416 { ISD::USUBSAT, MVT::v32i16, 1 },
2417 { ISD::USUBSAT, MVT::v64i8, 1 },
2466 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd
2467 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq
2468 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq
2469 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq
2480 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split
2481 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split
2548 { ISD::USUBSAT, MVT::v16i16, 1 },
2549 { ISD::USUBSAT, MVT::v32i8, 1 }
[all...] |
| X86ISelLowering.cpp | 961 setOperationAction(ISD::USUBSAT, MVT::v16i8, Legal);
965 setOperationAction(ISD::USUBSAT, MVT::v8i16, Legal);
967 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom);
968 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom);
1359 setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1363 setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1366 setOperationAction(ISD::USUBSAT, MVT::v8i32, Custom);
1368 setOperationAction(ISD::USUBSAT, MVT::v4i64, Custom);
1686 setOperationAction(ISD::USUBSAT, VT, HasBWI ? Legal : Custom);
22867 // cmpgt (xor X, SignMaskC) CmpC --> cmpeq (usubsat (CmpC+1), X),
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 455 case ISD::USUBSAT:
846 case ISD::USUBSAT:
|
| SelectionDAGDumper.cpp | 318 case ISD::USUBSAT: return "usubsat";
|
| LegalizeIntegerTypes.cpp | 170 case ISD::USUBSAT:
780 } else if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) {
798 // USUBSAT can always be promoted as long as we have zero-extended the args.
799 if (Opcode == ISD::USUBSAT)
800 return DAG.getNode(ISD::USUBSAT, dl, PromotedType, Op1Promoted,
2183 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
|
| TargetLowering.cpp | 7920 // umin(x,y) -> sub(x,usubsat(x,y))
7922 isOperationLegal(ISD::USUBSAT, VT)) {
7924 DAG.getNode(ISD::USUBSAT, DL, VT, Op0, Op1));
7927 // umax(x,y) -> add(x,usubsat(y,x))
7929 isOperationLegal(ISD::USUBSAT, VT)) {
7931 DAG.getNode(ISD::USUBSAT, DL, VT, Op1, Op0));
7964 if (Opcode == ISD::USUBSAT && isOperationLegal(ISD::UMAX, VT)) {
7987 case ISD::USUBSAT:
8018 if (Opcode == ISD::USUBSAT) {
|
| DAGCombiner.cpp | 1614 case ISD::USUBSAT: return visitSUBSAT(N);
2401 // fold (add (umax X, C), -C) --> (usubsat X, C)
2402 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
2409 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0),
3153 // Attempt to create a USUBSAT(LHS, RHS) node with DstVT, performing a
3162 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS);
3164 // If the LHS is zero-extended then we can perform the USUBSAT as DstVT by
3178 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS);
3182 // usubsat(a,b), optionally as a truncated type.
3185 !(!LegalOperations || hasOperation(ISD::USUBSAT, DstVT))
[all...] |
| SelectionDAG.cpp | 3474 case ISD::USUBSAT: {
3475 // The result of usubsat will never be larger than the LHS.
5071 case ISD::USUBSAT: return C1.usub_sat(C2);
5571 case ISD::USUBSAT:
5580 if (Opcode == ISD::SSUBSAT || Opcode == ISD::USUBSAT)
5901 case ISD::USUBSAT:
5926 case ISD::USUBSAT:
|
| LegalizeVectorTypes.cpp | 131 case ISD::USUBSAT:
1041 case ISD::USUBSAT:
3028 case ISD::USUBSAT:
|
| LegalizeDAG.cpp | 1137 case ISD::USUBSAT:
3374 case ISD::USUBSAT:
|
| SelectionDAGBuilder.cpp | 6438 setValue(&I, DAG.getNode(ISD::USUBSAT, sdl, Op1.getValueType(), Op1, Op2));
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 759 setOperationAction(ISD::USUBSAT, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 448 setOperationAction(ISD::USUBSAT, MVT::i32, Legal);
511 setOperationAction(ISD::USUBSAT, MVT::i16, Legal);
677 setOperationAction(ISD::USUBSAT, MVT::v2i16, Legal);
710 setOperationAction(ISD::USUBSAT, MVT::v4i16, Custom);
4548 case ISD::USUBSAT:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 321 setOperationAction(ISD::USUBSAT, VT, Legal);
1042 setOperationAction(ISD::USUBSAT, VT, Legal);
14047 return convertMergedOpToPredOp(N, ISD::USUBSAT, DAG, true);
14058 return DAG.getNode(ISD::USUBSAT, SDLoc(N), N->getValueType(0),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 201 setOperationAction(ISD::USUBSAT, MVT::i32, Custom);
4796 case ISD::USUBSAT: {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 222 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
283 setOperationAction(ISD::USUBSAT, VT, Legal);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 719 setOperationAction(ISD::USUBSAT, VT, Legal);
|
