HomeSort by: relevance | last modified time | path
    Searched refs:UVD_CGC_STATUS__MPC_DCLK__SHIFT (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h 167 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x00000014
uvd_4_2_sh_mask.h 206 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
uvd_5_0_sh_mask.h 222 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
uvd_6_0_sh_mask.h 224 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h 868 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
vcn_2_0_0_sh_mask.h 1888 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
vcn_2_5_sh_mask.h 1938 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14

Completed in 130 milliseconds