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    Searched refs:UVD_CGC_STATUS__MPC_SCLK_MASK (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h 168 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L
uvd_4_2_sh_mask.h 203 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
uvd_5_0_sh_mask.h 219 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
uvd_6_0_sh_mask.h 221 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h 899 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L
vcn_2_0_0_sh_mask.h 1918 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L
vcn_2_5_sh_mask.h 1968 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L

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