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    Searched refs:UVD_JRBC_STATUS__RB_JOB_DONE_MASK (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_jpeg_v2_5.c 447 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
448 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
464 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
465 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
amdgpu_jpeg_v2_0.c 679 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
680 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
688 SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
689 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h 765 #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L
vcn_2_0_0_sh_mask.h 748 #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L
vcn_2_5_sh_mask.h 751 #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L

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