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    Searched refs:UVD_MPC_SET_MUXA0__VARA_1_MASK (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h 500 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000fc0L
uvd_4_2_sh_mask.h 485 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0
uvd_5_0_sh_mask.h 517 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0
uvd_6_0_sh_mask.h 519 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0
uvd_7_0_sh_mask.h 606 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h 1113 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L
vcn_2_0_0_sh_mask.h 2619 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L
vcn_2_5_sh_mask.h 2854 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L

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