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Searched refs:UVD_SEMA_CMD__WR_PHASE_MASK (Results 1 - 7 of 7) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h	`626 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L`
uvd_4_2_sh_mask.h	`35 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30`
uvd_5_0_sh_mask.h	`35 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30`
uvd_6_0_sh_mask.h	`35 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`300 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L`
vcn_2_0_0_sh_mask.h	`3160 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L`
vcn_2_5_sh_mask.h	`2959 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L`

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