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    Searched refs:UVD_STATUS__VCPU_REPORT__SHIFT (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v7_0.c 898 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
1065 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
amdgpu_uvd_v6_0.c 813 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
amdgpu_vcn_v2_0.c 999 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
amdgpu_vcn_v2_5.c 1030 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h 695 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x00000001
uvd_4_2_sh_mask.h 634 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
uvd_5_0_sh_mask.h 696 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
uvd_6_0_sh_mask.h 698 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
uvd_7_0_sh_mask.h 754 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h 1281 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
vcn_2_0_0_sh_mask.h 2905 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
vcn_2_5_sh_mask.h 1737 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

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