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Searched refs:UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_5_0_sh_mask.h	`776 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa`
uvd_6_0_sh_mask.h	`774 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`492 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa`
vcn_2_0_0_sh_mask.h	`3248 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa`
vcn_2_5_sh_mask.h	`2122 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa`

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