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    Searched refs:UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_5_0_sh_mask.h 762 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
uvd_6_0_sh_mask.h 760 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h 485 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
vcn_2_0_0_sh_mask.h 3241 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
vcn_2_5_sh_mask.h 2115 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3

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