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Searched refs:UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_5_0_sh_mask.h	`769 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80`
uvd_6_0_sh_mask.h	`767 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`517 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L`
vcn_2_0_0_sh_mask.h	`3274 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L`
vcn_2_5_sh_mask.h	`2148 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L`

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