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    Searched refs:UndefReg (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600OptimizeVectorRegisters.cpp 53 std::vector<Register> UndefReg;
61 UndefReg.push_back(Chan);
162 if (CurrentUndexIdx >= Untouched->UndefReg.size())
165 ((*It).second, Untouched->UndefReg[CurrentUndexIdx++]));
192 std::vector<Register> UpdatedUndef = BaseRSI->UndefReg;
231 RSI->UndefReg = UpdatedUndef;
299 unsigned NeededUndefs = 4 - RSI.UndefReg.size();
314 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr);
SILowerI1Copies.cpp 428 unsigned UndefReg = createLaneMaskReg(MF);
430 UndefReg);
431 return UndefReg;
AMDGPUInstructionSelector.cpp 2003 Register UndefReg = MRI->createVirtualRegister(SrcRC);
2004 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg);
2008 .addReg(UndefReg)
2062 Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
2065 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg);
2069 .addReg(UndefReg)
SIISelLowering.cpp 11211 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT);
11214 UndefReg, Src0, SDValue());
11228 Src0 = UndefReg;
11229 Src1 = UndefReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CallFrameOptimization.cpp 543 Register UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass);
545 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg);
547 .addReg(UndefReg)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 310 Register UndefReg;
314 if (!UndefReg) {
316 UndefReg = Builder.buildUndef(SrcType).getReg(0);
318 Ops.push_back(UndefReg);
2836 Register UndefReg;
2838 if (UndefReg)
2839 return UndefReg;
2841 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0);
2842 return UndefReg;
LegalizerHelper.cpp 1431 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1433 Unmerges.push_back(UndefReg);

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