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    Searched refs:UseI (Results 1 - 18 of 18) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64StackTaggingPreRA.cpp 182 MachineInstr *UseI = &*(UI++);
183 if (isUncheckedLoadOrStoreOpcode(UseI->getOpcode())) {
185 unsigned OpIdx = TII->getLoadStoreImmIdx(UseI->getOpcode()) - 1;
186 if (UseI->getOperand(OpIdx).isReg() &&
187 UseI->getOperand(OpIdx).getReg() == TaggedReg) {
188 UseI->getOperand(OpIdx).ChangeToFrameIndex(FI);
189 UseI->getOperand(OpIdx).setTargetFlags(AArch64II::MO_TAGGED);
191 } else if (UseI->isCopy() &&
192 Register::isVirtualRegister(UseI->getOperand(0).getReg())) {
193 uncheckUsesOf(UseI->getOperand(0).getReg(), FI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600EmitClauseMarkers.cpp 194 for (MachineBasicBlock::iterator UseI = Def; UseI != BBEnd; ++UseI) {
195 AluInstCount += OccupiedDwords(*UseI);
197 if (!SubstituteKCacheBank(*UseI, KCacheBanks, false))
212 if (UseI->readsRegister(MOI->getReg(), &TRI))
216 if (UseI != Def && UseI->killsRegister(MOI->getReg(), &TRI))
AMDGPUSubtarget.cpp 820 MachineInstr *UseI = Use->getInstr();
835 } else if (UseI->isBundle()) {
838 MachineBasicBlock::const_instr_iterator I(UseI->getIterator());
839 MachineBasicBlock::const_instr_iterator E(UseI->getParent()->instr_end());
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MIRCanonicalizerPass.cpp 240 MachineBasicBlock::iterator UseI = BBE;
244 if (DefI != BBE && UseI != BBE)
253 UseI = BBI;
258 if (DefI == BBE || UseI == BBE)
265 UseI->dump();
270 MBB->splice(UseI, MBB, DefI);
276 auto UseI = llvm::find_if(MBB->instrs(), [&](MachineInstr &MI) -> bool {
280 if (UseI == MBB->instr_end())
287 [&]() -> MachineBasicBlock::iterator { return UseI; });
MachineCopyPropagation.cpp 285 const MachineInstr &UseI, unsigned UseIdx);
287 const MachineInstr &UseI,
387 const MachineInstr &Copy, const MachineInstr &UseI, unsigned UseIdx) {
391 UseI.getRegClassConstraint(UseIdx, TII, TRI))
394 // We don't process further if UseI is a COPY, since forward copy propagation
400 /// \param UseI based on the physical register class constraints of the opcode
403 const MachineInstr &UseI,
411 UseI.getRegClassConstraint(UseIdx, TII, TRI))
414 if (!UseI.isCopy())
423 /// RegClassB = COPY RegClassA // UseI paramete
    [all...]
SplitKit.cpp 222 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
223 UseI = UseSlots.begin();
238 if (UseI == UseE || *UseI >= Stop) {
247 BI.FirstInstr = *UseI;
249 do ++UseI;
250 while (UseI != UseE && *UseI < Stop);
251 BI.LastInstr = UseI[-1];
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonSplitDouble.cpp 253 MachineInstr *UseI = Op.getParent();
254 if (isFixedInstr(UseI))
256 for (unsigned i = 0, n = UseI->getNumOperands(); i < n; ++i) {
257 MachineOperand &MO = UseI->getOperand(i);
437 MachineInstr *UseI = U->getParent();
438 if (isFixedInstr(UseI)) {
441 for (auto &Op : UseI->operands()) {
452 if (UseI->isPHI()) {
453 const MachineBasicBlock *PB = UseI->getParent();
459 int32_t P = profit(UseI);
    [all...]
BitTracker.cpp 987 for (MachineInstr &UseI : MRI.use_nodbg_instructions(Reg))
988 UseQ.push(&UseI);
1106 MachineInstr &UseI = *UseQ.front();
1109 if (!InstrExec.count(&UseI))
1111 if (UseI.isPHI())
1112 visitPHI(UseI);
1113 else if (!UseI.isBranch())
1114 visitNonBranch(UseI);
1116 visitBranchesFrom(UseI);
HexagonLoopIdiomRecognition.cpp 601 bool classifyInst(Instruction *UseI, ValueSeq &Early, ValueSeq &Late);
1201 bool PolynomialMultiplyRecognize::classifyInst(Instruction *UseI,
1206 if (UseI->getOpcode() == Instruction::Select) {
1207 Value *TV = UseI->getOperand(1), *FV = UseI->getOperand(2);
1211 Early.insert(UseI);
1215 Late.insert(UseI);
1222 if (UseI->getNumOperands() == 0)
1226 for (auto &I : UseI->operands()) {
1247 Early.insert(UseI);
    [all...]
HexagonBitSimplify.cpp 976 MachineInstr *UseI = I->getParent();
977 if (UseI->isDebugValue())
979 if (UseI->isPHI()) {
980 assert(!UseI->getOperand(0).getSubReg());
981 Register DR = UseI->getOperand(0).getReg();
1220 MachineInstr &UseI = *I->getParent();
1221 if (UseI.isPHI() || UseI.isCopy()) {
1222 Register DefR = UseI.getOperand(0).getReg();
1227 if (!computeUsedBits(UseI, I.getOperandNo(), Used, B)
    [all...]
HexagonGenPredicate.cpp 240 MachineInstr *UseI = I->getParent();
241 if (isConvertibleToPredForm(UseI))
242 PUsers.insert(UseI);
  /src/external/apache2/llvm/dist/clang/lib/Driver/ToolChains/
BareMetal.cpp 75 bool UseI = (Arch == "rv32i") || (Arch == "rv32ic"); // ic => i
80 addMultilibFlag(UseI, "march=rv32i", Flags);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CmovConversion.cpp 323 [&](MachineInstr &UseI) {
324 return UseI.getOpcode() == X86::SUBREG_TO_REG;
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
LoopRotationUtils.cpp 739 for (User *UseI : IVOpnd->users()) {
740 auto *UserInst = cast<Instruction>(UseI);
SimplifyIndVar.cpp 1041 Instruction *UseI) {
1042 DefUserPair Key(Def, UseI);
1052 void updatePostIncRangeInfo(Value *Def, Instruction *UseI, ConstantRange R) {
1053 DefUserPair Key(Def, UseI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRegStackify.cpp 318 const MachineInstr *UseI = Use->getParent();
320 assert(UseI->getParent() == Insert->getParent());
341 for (const auto &PriorUse : UseI->uses()) {
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
LazyValueInfo.cpp 1909 if (auto *UseI = dyn_cast<Instruction>(U))
1910 if (!isa<PHINode>(UseI) || DT.dominates(ParentBB, UseI->getParent()))
1911 printResult(UseI->getParent());
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
LoopStrengthReduce.cpp 3124 auto UseI = find(Inc.UserInst->operands(), Inc.IVOperand);
3125 assert(UseI != Inc.UserInst->op_end() && "cannot find IV operand");
3126 IVIncSet.insert(UseI);
3261 User::op_iterator UseI =
3263 assert(UseI != UserInst->op_end() && "cannot find IV operand");
3264 if (IVIncSet.count(UseI)) {
3265 LLVM_DEBUG(dbgs() << "Use is in profitable chain: " << **UseI << '\n');

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