| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonOptAddrMode.cpp | 92 bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
96 bool updateAddUses(MachineInstr *AddMI, MachineInstr *UseMI);
187 MachineInstr &UseMI = *NodeAddr<StmtNode *>(IA).Addr->getCode();
191 MI.getParent() != UseMI.getParent())
194 const MCInstrDesc &UseMID = UseMI.getDesc();
196 HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset ||
197 getBaseWithLongOffset(UseMI) < 0)
201 if (UseMID.mayStore() && UseMI.getOperand(2).isReg() &&
202 UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg())
205 for (auto &Mo : UseMI.operands()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIFoldOperands.cpp | 24 MachineInstr *UseMI;
38 UseMI(MI), OpToFold(nullptr), ShrinkOpcode(ShrinkOp), UseOpNo(OpNo),
88 MachineInstr *UseMI,
151 const MachineInstr &UseMI,
154 if (TII->isInlineConstant(UseMI, OpNo, OpToFold))
157 unsigned Opc = UseMI.getOpcode();
175 const MachineInstr &UseMI,
181 if (TII->isMUBUF(UseMI))
182 return OpNo == AMDGPU::getNamedOperandIdx(UseMI.getOpcode(),
184 if (!TII->isFLATScratch(UseMI))
[all...] |
| SIFixSGPRCopies.cpp | 186 const auto *UseMI = MO.getParent();
187 if (UseMI == &MI)
189 if (MO.isDef() || UseMI->getParent() != MI.getParent() ||
190 UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END)
193 unsigned OpIdx = UseMI->getOperandNo(&MO);
194 if (OpIdx >= UseMI->getDesc().getNumOperands() ||
195 !TII->isOperandLegal(*UseMI, OpIdx, &Src))
788 const MachineInstr *UseMI = Use.getParent();
789 AllAGPRUses &= (UseMI->isCopy() &&
790 TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg())) |
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.h | 32 MachineBasicBlock::iterator &UseMI,
|
| Mips16RegisterInfo.cpp | 58 MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC,
63 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 187 MachineInstr *DefMI = nullptr, *UseMI = nullptr;
199 if (UseMI && UseMI != MI)
204 UseMI = MI;
207 if (!DefMI || !UseMI)
213 LIS.getInstructionIndex(*UseMI)))
217 // Assume there are stores between DefMI and UseMI.
223 << " into single use: " << *UseMI);
226 if (UseMI->readsWritesVirtualRegister(LI->reg(), &Ops).second)
229 MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS)
[all...] |
| MachineTraceMetrics.cpp | 649 // Get the input data dependencies that must be ready before UseMI can issue.
650 // Return true if UseMI has any physreg operands.
651 static bool getDataDeps(const MachineInstr &UseMI,
655 if (UseMI.isDebugInstr())
659 for (MachineInstr::const_mop_iterator I = UseMI.operands_begin(),
660 E = UseMI.operands_end(); I != E; ++I) {
673 Deps.push_back(DataDep(MRI, Reg, UseMI.getOperandNo(I)));
681 static void getPHIDeps(const MachineInstr &UseMI,
688 assert(UseMI.isPHI() && UseMI.getNumOperands() % 2 && "Bad PHI")
[all...] |
| OptimizePHIs.cpp | 157 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) {
158 if (!UseMI.isPHI() || !IsDeadPHICycle(&UseMI, PHIsInCycle))
|
| TargetSchedule.cpp | 186 const MachineInstr *UseMI, unsigned UseOperIdx) const {
193 if (UseMI) {
195 *UseMI, UseOperIdx);
225 if (!UseMI)
229 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
232 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
|
| DetectDeadLanes.cpp | 420 const MachineInstr &UseMI = *MO.getParent();
421 if (UseMI.isKill())
425 if (lowersToCopies(UseMI)) {
426 assert(UseMI.getDesc().getNumDefs() == 1);
427 const MachineOperand &Def = *UseMI.defs().begin();
434 if (lowersToCopies(UseMI)) {
436 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
438 LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI);
|
| MachineLICM.cpp | 949 for (MachineInstr &UseMI : MRI->use_instructions(CopyDstReg)) {
950 if (UseMI.mayStore() && isInvariantStore(UseMI, TRI, MRI))
1010 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
1012 if (UseMI.isPHI()) {
1015 if (CurLoop->contains(&UseMI))
1020 if (isExitBlock(UseMI.getParent()))
1025 if (UseMI.isCopy() && CurLoop->contains(&UseMI))
1026 Work.push_back(&UseMI);
[all...] |
| MachineSSAUpdater.cpp | 225 MachineInstr *UseMI = U.getParent();
227 if (UseMI->isPHI()) {
228 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U);
231 NewVR = GetValueInMiddleOfBlock(UseMI->getParent());
|
| RegisterScavenging.cpp | 290 MachineBasicBlock::iterator &UseMI) {
347 UseMI = RestorePointMI;
449 MachineBasicBlock::iterator &UseMI) {
494 if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {
511 TII->loadRegFromStackSlot(*MBB, UseMI, Reg, Scavenged[SI].FrameIndex,
513 II = std::prev(UseMI);
545 MachineBasicBlock::iterator UseMI;
546 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI);
557 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
558 Scavenged.Restore = &*std::prev(UseMI);
[all...] |
| TailDuplicator.cpp | 221 MachineInstr *UseMI = UseMO.getParent();
223 if (UseMI->isDebugValue()) {
228 UseMI->eraseFromParent();
231 if (UseMI->getParent() == DefBB && !UseMI->isPHI())
299 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
300 if (UseMI.isDebugValue())
302 if (UseMI.getParent() != BB)
|
| RegisterCoalescer.cpp | 866 MachineInstr *UseMI = MO.getParent();
867 unsigned OpNo = &MO - &UseMI->getOperand(0);
868 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI);
873 if (UseMI->isRegTiedToDefOperand(OpNo))
916 MachineInstr *UseMI = UseMO.getParent();
917 if (UseMI->isDebugValue()) {
923 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
934 if (UseMI == CopyMI)
936 if (!UseMI->isCopy())
938 if (UseMI->getOperand(0).getReg() != IntB.reg() |
[all...] |
| PeepholeOptimizer.cpp | 504 MachineInstr *UseMI = UseMO.getParent();
505 if (UseMI == &MI)
508 if (UseMI->isPHI()) {
534 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
537 MachineBasicBlock *UseMBB = UseMI->getParent();
540 if (!LocalMIs.count(UseMI))
577 MachineInstr *UseMI = UseMO->getParent();
578 MachineBasicBlock *UseMBB = UseMI->getParent();
589 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| Localizer.cpp | 126 MachineInstr &UseMI = *MOUse.getParent();
127 if (MRI->hasOneUse(Reg) && !UseMI.isPHI())
128 InsertMBB->insert(InsertMBB->SkipPHIsAndLabels(UseMI), LocalizedMI);
164 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
165 if (!UseMI.isPHI())
166 Users.insert(&UseMI);
|
| CombinerHelper.cpp | 404 MachineInstr &UseMI = *UseMO.getParent();
406 MachineBasicBlock *InsertBB = UseMI.getParent();
409 if (UseMI.isPHI()) {
481 for (auto &UseMI : MRI.use_nodbg_instructions(LoadValue.getReg())) {
482 if (UseMI.getOpcode() == TargetOpcode::G_SEXT ||
483 UseMI.getOpcode() == TargetOpcode::G_ZEXT ||
484 (UseMI.getOpcode() == TargetOpcode::G_ANYEXT)) {
487 if (MMO.isAtomic() && UseMI.getOpcode() != TargetOpcode::G_ANYEXT)
495 LLT UseTy = MRI.getType(UseMI.getOperand(0).getReg());
502 MRI.getType(UseMI.getOperand(0).getReg())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 122 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg);
123 if (UseMI->getParent() != MBB)
126 while (UseMI->isCopy() || UseMI->isInsertSubreg()) {
127 Reg = UseMI->getOperand(0).getReg();
130 UseMI = &*MRI->use_instr_nodbg_begin(Reg);
131 if (UseMI->getParent() != MBB)
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 203 /// StartMI. UseMI is set to the instruction where the search stopped.
209 MachineBasicBlock::iterator &UseMI);
218 /// \p UseMI.
221 MachineBasicBlock::iterator &UseMI);
|
| TargetSchedule.h | 172 /// when the operand indices are already known. UseMI may be NULL for an
175 const MachineInstr *UseMI, unsigned UseOperIdx)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEInstrInfo.h | 105 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
|
| VEInstrInfo.cpp | 546 bool VEInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
606 LLVM_DEBUG(dbgs() << "checking UseMI\n");
607 LLVM_DEBUG(UseMI.dump());
629 switch (UseMI.getOpcode()) {
672 LLVM_DEBUG(dbgs() << "checking UseMI operands\n");
676 if (UseMI.getOperand(1).getReg() == Reg) {
679 assert(UseMI.getOperand(2).getReg() == Reg);
693 if (UseMI.getOperand(1).getReg() == Reg) {
694 // Check immediate value whether it matchs to the UseMI instruction.
700 assert(UseMI.getOperand(2).getReg() == Reg)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCVSXSwapRemoval.cpp | 677 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
678 int UseIdx = SwapMap[&UseMI];
690 LLVM_DEBUG(UseMI.dump());
699 Register SwapDefReg = UseMI.getOperand(0).getReg();
711 LLVM_DEBUG(UseMI.dump());
743 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
744 int UseIdx = SwapMap[&UseMI];
785 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
786 int UseIdx = SwapMap[&UseMI];
790 LLVM_DEBUG(UseMI.dump())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86SpeculativeLoadHardening.cpp | 1792 for (MachineInstr &UseMI : MRI->use_instructions(DefReg)) {
1795 if (HardenedInstrs.count(&UseMI)) {
1796 if (!X86InstrInfo::isDataInvariantLoad(UseMI) || isEFLAGSDefLive(UseMI)) {
1800 assert(X86InstrInfo::isDataInvariant(UseMI) &&
1807 const MCInstrDesc &Desc = UseMI.getDesc();
1814 UseMI.getOperand(MemRefBeginIdx + X86::AddrBaseReg);
1816 UseMI.getOperand(MemRefBeginIdx + X86::AddrIndexReg);
1832 if (!X86InstrInfo::isDataInvariant(UseMI) || UseMI.getParent() != MI.getParent() |
[all...] |
