| /src/crypto/external/apache2/openssl/dist/crypto/sm3/asm/ |
| sm3-riscv64-zvksh.pl | 67 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
82 @{[vle32_v $V0, $CTX]}
83 @{[vrev8_v $V0, $V0]}
88 @{[vmv_v_v $V2, $V0]}
104 @{[vsm3c_vi $V0, $V6, 0]}
105 @{[vsm3c_vi $V0, $V4, 1]}
111 @{[vsm3c_vi $V0, $V4, 2]}
113 @{[vsm3c_vi $V0, $V4, 3]}
115 @{[vsm3c_vi $V0, $V8, 4]
[all...] |
| /src/crypto/external/apache2/openssl/dist/crypto/modes/asm/ |
| ghash-riscv64-zvkg.pl | 90 my ($Htable,$H,$V0) = ("a0","a1","v0");
98 @{[vle64_v $V0, $H]} # vle64.v v0, (a1)
99 @{[vrev8_v $V0, $V0]} # vrev8.v v0, v0
100 @{[vse64_v $V0, $Htable]} # vse64.v v0, (a0
[all...] |
| ghash-riscv64-zvkb-zvbc.pl | 69 my ($V0,$V1,$V2,$V3,$V4,$V5,$V6) = ("v0","v1","v2","v3","v4","v5","v6");
100 @{[vmv_v_i $V0, 2]} # vmv.v.i v0, 2
101 @{[vor_vv_v0t $V1, $V1, $V4]} # vor.vv v1, v1, v4, v0.t
104 @{[vmv_v_v $V0, $V3]} # vmv.v.v v0, v3
106 @{[vmerge_vim $V3, $V3, 3]} # vmerge.vim v3, v3, 3, v0
107 @{[vmv_v_v $V0, $V3]} # vmv.v.v v0, v
[all...] |
| aes-gcm-riscv64-zvkb-zvkg-zvkned.pl | 87 my ($CTR_MASK) = ("v0");
88 my ($INPUT_PADDING_MASK) = ("v0");
89 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
575 # Compute the final tag into v0 from the partial tag v20.
587 @{[vmv_v_v $V0, $V20]}
588 @{[vgmul_vv $V0, $V1]}
595 @{[vghsh_vv $V0, $V1, $V4]}
680 @{[vse32_v $V0, $XIP]}
729 @{[vse32_v $V0, $XIP]}
778 @{[vse32_v $V0, $XIP]
[all...] |
| /src/crypto/external/apache2/openssl/dist/crypto/sha/asm/ |
| sha256-riscv64-zvkb-zvknha_or_zvknhb.pl | 63 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
144 # Setup v0 mask for the vmerge to replace the first word (idx==0) in key-scheduling.
147 @{[vmv_v_i $V0, 0x01]}
178 @{[vmerge_vvm $V5, $V3, $V2, $V0]}
185 @{[vmerge_vvm $V5, $V4, $V3, $V0]}
192 @{[vmerge_vvm $V5, $V1, $V4, $V0]}
199 @{[vmerge_vvm $V5, $V2, $V1, $V0]}
206 @{[vmerge_vvm $V5, $V3, $V2, $V0]}
213 @{[vmerge_vvm $V5, $V4, $V3, $V0]}
220 @{[vmerge_vvm $V5, $V1, $V4, $V0]}
[all...] |
| sha512-riscv64-zvkb-zvknhb.pl | 63 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
103 # Setup v0 mask for the vmerge to replace the first word (idx==0) in key-scheduling.
106 @{[vmv_v_i $V0, 0x01]}
143 @{[vmerge_vvm $V18, $V14, $V12, $V0]}
152 @{[vmerge_vvm $V18, $V16, $V14, $V0]}
161 @{[vmerge_vvm $V18, $V10, $V16, $V0]}
170 @{[vmerge_vvm $V18, $V12, $V10, $V0]}
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 76 Register V0 = RegInfo.createVirtualRegister(RC);
83 // lui $v0, %hi(%neg(%gp_rel(fname)))
84 // daddu $v1, $v0, $t9
87 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
89 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
99 // lui $v0, %hi(__gnu_local_gp)
100 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
101 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
103 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
112 // lui $v0, %hi(%neg(%gp_rel(fname))
[all...] |
| Mips16ISelDAGToDAG.cpp | 75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF);
78 V0 = RegInfo.createVirtualRegister(RC);
83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
|
| /src/external/gpl3/gdb.old/dist/sim/common/ |
| sim-trace.h | 525 #define TRACE_ALU_INPUT1(V0) \
528 trace_input_word1 (SD, CPU, TRACE_ALU_IDX, (V0)); \
531 #define TRACE_ALU_INPUT2(V0,V1) \
534 trace_input_word2 (SD, CPU, TRACE_ALU_IDX, (V0), (V1)); \
537 #define TRACE_ALU_INPUT3(V0,V1,V2) \
540 trace_input_word3 (SD, CPU, TRACE_ALU_IDX, (V0), (V1), (V2)); \
543 #define TRACE_ALU_INPUT4(V0,V1,V2,V3) \
546 trace_input_word4 (SD, CPU, TRACE_ALU_IDX, (V0), (V1), (V2), (V3)); \
577 #define TRACE_BRANCH_INPUT1(V0) \
580 trace_input_word1 (SD, CPU, TRACE_BRANCH_IDX, (V0)); \
[all...] |
| /src/external/gpl3/gdb/dist/sim/common/ |
| sim-trace.h | 525 #define TRACE_ALU_INPUT1(V0) \
528 trace_input_word1 (SD, CPU, TRACE_ALU_IDX, (V0)); \
531 #define TRACE_ALU_INPUT2(V0,V1) \
534 trace_input_word2 (SD, CPU, TRACE_ALU_IDX, (V0), (V1)); \
537 #define TRACE_ALU_INPUT3(V0,V1,V2) \
540 trace_input_word3 (SD, CPU, TRACE_ALU_IDX, (V0), (V1), (V2)); \
543 #define TRACE_ALU_INPUT4(V0,V1,V2,V3) \
546 trace_input_word4 (SD, CPU, TRACE_ALU_IDX, (V0), (V1), (V2), (V3)); \
577 #define TRACE_BRANCH_INPUT1(V0) \
580 trace_input_word1 (SD, CPU, TRACE_BRANCH_IDX, (V0)); \
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonVectorPrint.cpp | 74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) ||
81 if (R >= Hexagon::V0 && R <= Hexagon::V31) {
86 return S[R-Hexagon::V0];
183 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) {
184 LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n');
188 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1,
190 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2,
|
| /src/external/gpl2/groff/dist/src/roff/troff/ |
| div.cpp | 57 : prev(0), nm(s), vertical_position(V0), high_water_mark(V0),
60 marked_place(V0)
70 : pre_extra(V0), post_extra(V0), pre(vs), post(post_vs)
80 if (n < V0) {
90 if (n < V0)
322 else if (n + vertical_position < V0)
349 if (pt->position >= V0) {
409 else if (v.post > V0) {
[all...] |
| column.cpp | 176 return V0;
181 return V0;
186 return V0;
232 current = V0;
283 : bottom(V0), col(0), tail(&col), out(0)
400 bottom = V0;
421 vunits vpos(V0);
432 bottom = V0;
441 return V0;
475 if (v <= V0) {
[all...] |
| /src/lib/libm/src/ |
| e_j1.c | 54 * V(z) = 1 + v0[0]*z + ... + v0[4]*z^5
136 static const double V0[5] = {
189 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4]))));
|
| e_j1f.c | 97 static const float V0[5] = {
150 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4]))));
|
| /src/external/bsd/pcc/dist/pcc/arch/mips/ |
| order.c | 177 { NRES, V0 },
197 { NRES, V0 },
|
| macdefs.h | 140 #define V0 2
230 F0 : V0)
263 { V0V1, -1 }, /* $v0 */ \
297 { V0, V1, -1 }, /* $v0:$v1 */ \
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| VectorCombine.cpp | 320 // opcode (extelt V0, Ext0), (ext V1, Ext1) -->
321 // extelt (opcode (splat V0, Ext0), V1), Ext1
341 // opcode (extelt V0, C0), (extelt V1, C1) --> extelt (opcode V0, V1), C
405 /// cmp (ext0 V0, C), (ext1 V1, C)
413 // cmp Pred (extelt V0, C), (extelt V1, C) --> extelt (cmp Pred V0, V1), C
416 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand();
417 Value *VecCmp = Builder.CreateCmp(Pred, V0, V1);
424 /// bo (ext0 V0, C), (ext1 V1, C
[all...] |
| /src/external/gpl3/gdb/dist/sim/v850/ |
| v850-sim.h | 533 #define TRACE_FP_INPUT_FPU1(V0) \
538 sim_fpu_to64 (&f0, (V0)); \
543 #define TRACE_FP_INPUT_FPU2(V0, V1) \
548 sim_fpu_to64 (&f0, (V0)); \
554 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
559 sim_fpu_to64 (&f0, (V0)); \
566 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
570 int d0 = (V0); \
582 #define TRACE_FP_INPUT_WORD2(V0, V1) \
585 trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1));
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/v850/ |
| v850-sim.h | 533 #define TRACE_FP_INPUT_FPU1(V0) \
538 sim_fpu_to64 (&f0, (V0)); \
543 #define TRACE_FP_INPUT_FPU2(V0, V1) \
548 sim_fpu_to64 (&f0, (V0)); \
554 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
559 sim_fpu_to64 (&f0, (V0)); \
566 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
570 int d0 = (V0); \
582 #define TRACE_FP_INPUT_WORD2(V0, V1) \
585 trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1));
[all...] |
| /src/crypto/external/apache2/openssl/dist/crypto/chacha/asm/ |
| chacha-riscv64-v-zbb.pl | 92 $V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7, $V8, $V9, $V10,
278 # init chacha const states into $V0~$V3
281 @{[vmv_v_x $V0, $CONST_DATA0]}
328 # - $V0~$V15 for chacha states.
338 $V0, $V4, $V8, $V12,
349 $V0, $V5, $V10, $V15,
369 @{[vadd_vx $V0, $V0, $T0]}
397 @{[vxor_vv $V16, $V16, $V0]}
434 @{[vid_v $V0]}
[all...] |
| /src/crypto/external/apache2/openssl/dist/crypto/aes/asm/ |
| aes-riscv64-zvbb-zvkg-zvkned.pl | 76 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
120 @{[vbrev8_v $V0, $V28]}
124 @{[vaesz_vs $V16, $V0]}
161 @{[vmv_v_i $V0, 0]}
163 @{[vmv_v_x $V0, $T0]}
165 @{[vbrev8_v $V0, $V0]}
168 @{[vaesz_vs $V20, $V0]}
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| LibCallsShrinkWrap.cpp | 470 Constant *V0 = ConstantFP::get(CI->getContext(), APFloat(0.0f));
474 V0 = ConstantExpr::getFPExtend(V0, Exp->getType());
477 Value *Cond0 = BBBuilder.CreateFCmp(CmpInst::FCMP_OLE, Base, V0);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/ |
| RISCVDisassembler.cpp | 170 MCRegister Reg = RISCV::V0 + RegNo;
188 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
208 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
228 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
242 Reg = RISCV::V0;
|
| /src/external/apache2/llvm/dist/clang/lib/Driver/ToolChains/ |
| Darwin.h | 428 bool isIPhoneOSVersionLT(unsigned V0, unsigned V1 = 0,
431 return TargetVersion < VersionTuple(V0, V1, V2);
438 bool isMacosxVersionLT(unsigned V0, unsigned V1 = 0, unsigned V2 = 0) const {
448 : TargetVersion) < VersionTuple(V0, V1, V2);
|
