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      1 /*	$NetBSD: icsidereg.h,v 1.3 2002/09/15 11:00:11 bjh21 Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1997 Mark Brinicombe
      5  * Copyright (c) 1997 Causality Limited
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. All advertising materials mentioning features or use of this software
     16  *    must display the following acknowledgement:
     17  *	This product includes software developed by Mark Brinicombe
     18  *	for the NetBSD Project.
     19  * 4. The name of the author may not be used to endorse or promote products
     20  *    derived from this software without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     32  */
     33 
     34 /*
     35  * Registers and address offsets for the ICS IDE card.
     36  */
     37 
     38 /* ID register, read 4 consecutive words and extract ID from bit 0 */
     39 #define ID_REGISTER_OFFSET		0x2280	/* byte offset from fast base */
     40 
     41 #define REGISTER_SPACING_SHIFT		6
     42 #define IDE_REGISTER_SPACE		0x200
     43 #define AUX_REGISTER_SPACE		4
     44 #define IRQ_REGISTER_SPACE		4
     45 #define ID_REGISTER_SPACE		4
     46 #define IRQ_STATUS_REGISTER_MASK	0x01
     47 
     48 /* IDE drive registers */
     49 
     50 #define ICSIDE_MAX_CHANNELS	2
     51 
     52 /* ARCIN V5 registers */
     53 #define V5_IDE_BASE			0x2800	/* byte offset from base */
     54 #define V5_AUX_BASE			0x2a80	/* byte offset from base */
     55 #define V5_IRQ_BASE			0x0004	/* byte offset from base */
     56 #define V5_IRQSTAT_BASE			0x0000	/* byte offset from base */
     57 
     58 /* ARCIN V6 registers */
     59 #define V6_ADDRLATCH			0x0000
     60 #define V6_ADDRLATCH_DMACHAN		0x01 /* XXX doc is unclear, poss 0x02*/
     61 #define V6_ADDRLATCH_EASI		0x20 /* EASI space enable */
     62 
     63 #define V6_P_IDE_BASE			0x2000	/* byte offset from base */
     64 #define V6_P_AUX_BASE			0x2380	/* byte offset from base */
     65 #define V6_P_IRQ_BASE			0x2200	/* byte offset from base */
     66 #define V6_P_IRQSTAT_BASE		0x2290	/* byte offset from base */
     67 
     68 #define V6_S_IDE_BASE			0x3000	/* byte offset from base */
     69 #define V6_S_AUX_BASE			0x3380	/* byte offset from base */
     70 #define V6_S_IRQ_BASE			0x3200	/* byte offset from base */
     71 #define V6_S_IRQSTAT_BASE		0x3290	/* byte offset from base */
     72